Simulation Results: adc_ctrl

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 70.41 %
  • code
  • 96.81 %
  • assert
  • 96.60 %
  • func
  • 17.81 %
  • line
  • 99.02 %
  • branch
  • 98.45 %
  • cond
  • 94.67 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 4.500s 6049.207us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 3.010s 1005.204us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 2.180s 395.854us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 37.580s 22635.163us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.260s 975.477us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.360s 458.810us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 2.180s 395.854us 1 1 100.00
adc_ctrl_csr_aliasing 2.260s 975.477us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 77.830s 34912.363us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 57.400s 55853.805us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 28.690s 54522.663us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 129.310s 52788.009us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 47.420s 50000.694us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 20.650s 22028.242us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 20.500s 18914.615us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 18.320s 41578.202us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 3.390s 5474.417us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 51.660s 24550.017us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 95.400s 90647.927us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 58.790s 84365.090us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.110s 341.031us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.460s 398.007us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.900s 1253.995us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.900s 1253.995us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.010s 1005.204us 1 1 100.00
adc_ctrl_csr_rw 2.180s 395.854us 1 1 100.00
adc_ctrl_csr_aliasing 2.260s 975.477us 1 1 100.00
adc_ctrl_same_csr_outstanding 9.680s 2478.601us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.010s 1005.204us 1 1 100.00
adc_ctrl_csr_rw 2.180s 395.854us 1 1 100.00
adc_ctrl_csr_aliasing 2.260s 975.477us 1 1 100.00
adc_ctrl_same_csr_outstanding 9.680s 2478.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 16.400s 8244.468us 1 1 100.00
adc_ctrl_tl_intg_err 6.550s 4440.424us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 6.550s 4440.424us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 9.530s 22502.748us 1 1 100.00