Simulation Results: aes/masked

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.56 %
  • code
  • 94.21 %
  • assert
  • 98.23 %
  • func
  • 73.23 %
  • block
  • 94.35 %
  • line
  • 95.93 %
  • branch
  • 87.35 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 96.551us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 128.005us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 65.160us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 83.911us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 468.432us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 321.975us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 61.303us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 83.911us 1 1 100.00
aes_csr_aliasing 3.000s 321.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 128.005us 1 1 100.00
aes_config_error 3.000s 147.095us 1 1 100.00
aes_stress 5.000s 128.044us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 128.005us 1 1 100.00
aes_config_error 3.000s 147.095us 1 1 100.00
aes_stress 5.000s 128.044us 1 1 100.00
back2back 2 2 100.00
aes_stress 5.000s 128.044us 1 1 100.00
aes_b2b 6.000s 533.811us 1 1 100.00
backpressure 1 1 100.00
aes_stress 5.000s 128.044us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 128.005us 1 1 100.00
aes_config_error 3.000s 147.095us 1 1 100.00
aes_stress 5.000s 128.044us 1 1 100.00
aes_alert_reset 6.000s 1349.051us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 107.260us 1 1 100.00
aes_config_error 3.000s 147.095us 1 1 100.00
aes_alert_reset 6.000s 1349.051us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 181.402us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 16.000s 807.217us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 6.000s 1349.051us 1 1 100.00
stress 1 1 100.00
aes_stress 5.000s 128.044us 1 1 100.00
sideload 2 2 100.00
aes_stress 5.000s 128.044us 1 1 100.00
aes_sideload 4.000s 235.285us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 5.000s 424.199us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 41.000s 11852.576us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 102.041us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 185.585us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 185.585us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 65.160us 1 1 100.00
aes_csr_rw 2.000s 83.911us 1 1 100.00
aes_csr_aliasing 3.000s 321.975us 1 1 100.00
aes_same_csr_outstanding 2.000s 103.304us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 65.160us 1 1 100.00
aes_csr_rw 2.000s 83.911us 1 1 100.00
aes_csr_aliasing 3.000s 321.975us 1 1 100.00
aes_same_csr_outstanding 2.000s 103.304us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 233.838us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 5.000s 215.813us 0 1 0.00
aes_control_fi 2.000s 54.966us 1 1 100.00
aes_cipher_fi 3.000s 47.330us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 8.000s 223.860us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 8.000s 223.860us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 8.000s 223.860us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 8.000s 223.860us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 255.880us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 1913.995us 1 1 100.00
aes_tl_intg_err 3.000s 127.616us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 127.616us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 6.000s 1349.051us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 8.000s 223.860us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 8.000s 223.860us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 128.005us 1 1 100.00
aes_stress 5.000s 128.044us 1 1 100.00
aes_alert_reset 6.000s 1349.051us 1 1 100.00
aes_core_fi 3.000s 74.299us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 147.095us 1 1 100.00
aes_stress 5.000s 128.044us 1 1 100.00
aes_core_fi 3.000s 74.299us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 8.000s 223.860us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 66.636us 1 1 100.00
aes_stress 5.000s 128.044us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 5.000s 128.044us 1 1 100.00
aes_sideload 4.000s 235.285us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 66.636us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 66.636us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 66.636us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 66.636us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 66.636us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 5.000s 128.044us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 5.000s 128.044us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 5.000s 215.813us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 5.000s 215.813us 0 1 0.00
aes_control_fi 2.000s 54.966us 1 1 100.00
aes_cipher_fi 3.000s 47.330us 1 1 100.00
aes_ctr_fi 2.000s 91.369us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 5.000s 215.813us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 5.000s 215.813us 0 1 0.00
aes_control_fi 2.000s 54.966us 1 1 100.00
aes_cipher_fi 3.000s 47.330us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 47.330us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 5.000s 215.813us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 5.000s 215.813us 0 1 0.00
aes_control_fi 2.000s 54.966us 1 1 100.00
aes_ctr_fi 2.000s 91.369us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 5.000s 215.813us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 5.000s 215.813us 0 1 0.00
aes_control_fi 2.000s 54.966us 1 1 100.00
aes_cipher_fi 3.000s 47.330us 1 1 100.00
aes_ctr_fi 2.000s 91.369us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 6.000s 1349.051us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 5.000s 215.813us 0 1 0.00
aes_control_fi 2.000s 54.966us 1 1 100.00
aes_cipher_fi 3.000s 47.330us 1 1 100.00
aes_ctr_fi 2.000s 91.369us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 5.000s 215.813us 0 1 0.00
aes_control_fi 2.000s 54.966us 1 1 100.00
aes_cipher_fi 3.000s 47.330us 1 1 100.00
aes_ctr_fi 2.000s 91.369us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 5.000s 215.813us 0 1 0.00
aes_control_fi 2.000s 54.966us 1 1 100.00
aes_ctr_fi 2.000s 91.369us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 5.000s 215.813us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 5.000s 215.813us 0 1 0.00
aes_control_fi 2.000s 54.966us 1 1 100.00
aes_cipher_fi 3.000s 47.330us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 87.160us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 11001099278505192484026615411008147464932819695711167242031476937579111659046 6701
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_FATAL (csr_utils_pkg.sv:623) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=53) 1 test run
aes_stress_all 37753054674518492558025654257246705948209744511570167267111477716422570689500 143093
UVM_INFO @ 11852575758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 24222737750306167912100622260730823179299425750216776991259929523159739751478 111
UVM_INFO @ 87159529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---