Simulation Results: aes/unmasked

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.23 %
  • code
  • 89.56 %
  • assert
  • 97.92 %
  • func
  • 74.19 %
  • block
  • 90.02 %
  • line
  • 92.53 %
  • branch
  • 81.07 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 125.829us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 141.433us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 57.258us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 62.403us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 164.292us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 580.700us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 112.503us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 62.403us 1 1 100.00
aes_csr_aliasing 3.000s 580.700us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 141.433us 1 1 100.00
aes_config_error 8.000s 89.799us 1 1 100.00
aes_stress 4.000s 97.377us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 141.433us 1 1 100.00
aes_config_error 8.000s 89.799us 1 1 100.00
aes_stress 4.000s 97.377us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 97.377us 1 1 100.00
aes_b2b 11.000s 437.049us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 97.377us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 141.433us 1 1 100.00
aes_config_error 8.000s 89.799us 1 1 100.00
aes_stress 4.000s 97.377us 1 1 100.00
aes_alert_reset 2.000s 65.227us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 110.817us 1 1 100.00
aes_config_error 8.000s 89.799us 1 1 100.00
aes_alert_reset 2.000s 65.227us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 135.409us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 6.000s 1009.371us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 65.227us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 97.377us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 97.377us 1 1 100.00
aes_sideload 4.000s 162.779us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 84.689us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 7.000s 1307.671us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 56.253us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 5.000s 1383.339us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 5.000s 1383.339us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 57.258us 1 1 100.00
aes_csr_rw 2.000s 62.403us 1 1 100.00
aes_csr_aliasing 3.000s 580.700us 1 1 100.00
aes_same_csr_outstanding 2.000s 91.323us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 57.258us 1 1 100.00
aes_csr_rw 2.000s 62.403us 1 1 100.00
aes_csr_aliasing 3.000s 580.700us 1 1 100.00
aes_same_csr_outstanding 2.000s 91.323us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 181.991us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 243.515us 0 1 0.00
aes_control_fi 2.000s 67.013us 1 1 100.00
aes_cipher_fi 1.000s 48.152us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 81.517us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 81.517us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 81.517us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 81.517us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 106.240us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 2175.002us 1 1 100.00
aes_tl_intg_err 4.000s 786.882us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 4.000s 786.882us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 65.227us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 81.517us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 81.517us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 141.433us 1 1 100.00
aes_stress 4.000s 97.377us 1 1 100.00
aes_alert_reset 2.000s 65.227us 1 1 100.00
aes_core_fi 3.000s 124.042us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 8.000s 89.799us 1 1 100.00
aes_stress 4.000s 97.377us 1 1 100.00
aes_core_fi 3.000s 124.042us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 81.517us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 65.160us 1 1 100.00
aes_stress 4.000s 97.377us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 97.377us 1 1 100.00
aes_sideload 4.000s 162.779us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 65.160us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 65.160us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 65.160us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 65.160us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 65.160us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 97.377us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 97.377us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 243.515us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 243.515us 0 1 0.00
aes_control_fi 2.000s 67.013us 1 1 100.00
aes_cipher_fi 1.000s 48.152us 1 1 100.00
aes_ctr_fi 2.000s 210.163us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 243.515us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 243.515us 0 1 0.00
aes_control_fi 2.000s 67.013us 1 1 100.00
aes_cipher_fi 1.000s 48.152us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 48.152us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 243.515us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 243.515us 0 1 0.00
aes_control_fi 2.000s 67.013us 1 1 100.00
aes_ctr_fi 2.000s 210.163us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 243.515us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 243.515us 0 1 0.00
aes_control_fi 2.000s 67.013us 1 1 100.00
aes_cipher_fi 1.000s 48.152us 1 1 100.00
aes_ctr_fi 2.000s 210.163us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 65.227us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 243.515us 0 1 0.00
aes_control_fi 2.000s 67.013us 1 1 100.00
aes_cipher_fi 1.000s 48.152us 1 1 100.00
aes_ctr_fi 2.000s 210.163us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 243.515us 0 1 0.00
aes_control_fi 2.000s 67.013us 1 1 100.00
aes_cipher_fi 1.000s 48.152us 1 1 100.00
aes_ctr_fi 2.000s 210.163us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 243.515us 0 1 0.00
aes_control_fi 2.000s 67.013us 1 1 100.00
aes_ctr_fi 2.000s 210.163us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 243.515us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 243.515us 0 1 0.00
aes_control_fi 2.000s 67.013us 1 1 100.00
aes_cipher_fi 1.000s 48.152us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 15.000s 1500.349us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 25166261559438590958280801464711713572542343081403897027353995854678438871747 3681
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all 115195887434612767207507624017146994510126561032427578906996011878588937882280 11486
UVM_INFO @ 1307671445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 73643438222901813433348965024991167370216454813953173063870436848975922231205 634
UVM_INFO @ 1500349367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---