Simulation Results

Simulation Results: chip

25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
71.87 %

code
75.79 %

assert
96.49 %

func
43.33 %

line
93.69 %

branch
93.14 %

cond
88.86 %

toggle
69.91 %

FSM
33.33 %

Validation stages

V1		100.00%
V2		84.03%
V2S		50.00%
V3		58.33%
unmapped		12.50%

17/17 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				3	3	100.00
	chip_sw_example_rom	117.980s	2380.244us	1	1	100.00
	chip_sw_example_manufacturer	197.160s	2907.094us	1	1	100.00
	chip_sw_example_concurrency	255.680s	3354.032us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	366.130s	8991.695us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	891.920s	11363.323us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	1459.240s	20269.451us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	4596.200s	35851.691us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	586.660s	9730.054us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	4596.200s	35851.691us	1	1	100.00
	chip_csr_rw	891.920s	11363.323us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	8.370s	207.062us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	391.030s	3966.479us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	391.030s	3966.479us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	391.030s	3966.479us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	488.750s	3862.415us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	488.750s	3862.415us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	444.060s	4334.800us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	494.680s	4278.025us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	462.030s	3960.492us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	2114.860s	12802.993us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	393.080s	3391.186us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	376.100s	4485.355us	1	1	100.00

221/263 passed

84.03 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	454.600s	9656.975us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	454.600s	9656.975us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	237.400s	3389.134us	1	1	100.00
chip_sw_sleep_pin_wake				0	1	0.00
	chip_sw_sleep_pin_wake	185.290s	2495.763us	0	1	0.00
chip_sw_sleep_pin_retention				0	1	0.00
	chip_sw_sleep_pin_retention	181.350s	2838.223us	0	1	0.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	606.050s	8138.544us	1	1	100.00
	chip_tap_straps_testunlock0	230.630s	3365.474us	1	1	100.00
	chip_tap_straps_rma	435.970s	6582.159us	1	1	100.00
	chip_tap_straps_prod	797.680s	9469.517us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	610.000s	6164.372us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	610.000s	6164.372us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	738.440s	7653.717us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1021.460s	9229.355us	0	1	0.00
chip_sw_ast_sys_clk_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4303.730s	18700.676us	1	1	100.00
	chip_sw_aes_enc_jitter_en	185.030s	2909.980us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	788.120s	5780.516us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	231.380s	3307.339us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	2015.130s	11934.188us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	216.980s	2754.126us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	499.830s	4682.816us	1	1	100.00
	chip_sw_clkmgr_jitter	246.870s	2688.116us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	214.190s	3194.330us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				1	2	50.00
	chip_sw_sensor_ctrl_alert	818.270s	7805.786us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	192.740s	2796.431us	0	1	0.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	262.600s	2557.925us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				0	1	0.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	192.740s	2796.431us	0	1	0.00
chip_sw_smoketest				16	16	100.00
	chip_sw_aes_smoketest	233.940s	3182.370us	1	1	100.00
	chip_sw_aon_timer_smoketest	239.720s	2679.937us	1	1	100.00
	chip_sw_clkmgr_smoketest	257.580s	2317.537us	1	1	100.00
	chip_sw_csrng_smoketest	211.860s	2584.940us	1	1	100.00
	chip_sw_entropy_src_smoketest	1120.960s	6994.672us	1	1	100.00
	chip_sw_gpio_smoketest	230.920s	2677.667us	1	1	100.00
	chip_sw_hmac_smoketest	240.910s	3122.734us	1	1	100.00
	chip_sw_kmac_smoketest	280.650s	3436.088us	1	1	100.00
	chip_sw_otbn_smoketest	1400.470s	8413.683us	1	1	100.00
	chip_sw_pwrmgr_smoketest	445.610s	5189.343us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	289.020s	5483.499us	1	1	100.00
	chip_sw_rv_plic_smoketest	210.180s	3163.449us	1	1	100.00
	chip_sw_rv_timer_smoketest	216.400s	2624.984us	1	1	100.00
	chip_sw_rstmgr_smoketest	178.720s	2266.238us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	201.300s	2563.572us	1	1	100.00
	chip_sw_uart_smoketest	195.210s	2443.813us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	208.210s	3081.708us	1	1	100.00
chip_sw_rom_functests				1	1	100.00
	rom_keymgr_dpe_functest	354.130s	4083.532us	1	1	100.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	21494.470s	127296.874us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3775.610s	15490.398us	1	1	100.00
chip_sw_rom_raw_unlock				1	1	100.00
	rom_raw_unlock	553.390s	9379.108us	1	1	100.00
chip_sw_power_idle_load				1	1	100.00
	chip_sw_power_idle_load	444.940s	3764.732us	1	1	100.00
chip_sw_power_sleep_load				1	1	100.00
	chip_sw_power_sleep_load	314.580s	9599.860us	1	1	100.00
chip_sw_exit_test_unlocked_bootstrap				0	1	0.00
	chip_sw_exit_test_unlocked_bootstrap	13200.144s	0.000us	0	1	0.00
tl_d_oob_addr_access				1	1	100.00
	chip_tl_errors	367.270s	8863.362us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	chip_tl_errors	367.270s	8863.362us	1	1	100.00
tl_d_outstanding_access				3	4	75.00
	chip_csr_aliasing	4596.200s	35851.691us	1	1	100.00
	chip_same_csr_outstanding	270.670s	4864.331us	0	1	0.00
	chip_csr_hw_reset	366.130s	8991.695us	1	1	100.00
	chip_csr_rw	891.920s	11363.323us	1	1	100.00
tl_d_partial_access				3	4	75.00
	chip_csr_aliasing	4596.200s	35851.691us	1	1	100.00
	chip_same_csr_outstanding	270.670s	4864.331us	0	1	0.00
	chip_csr_hw_reset	366.130s	8991.695us	1	1	100.00
	chip_csr_rw	891.920s	11363.323us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	24.700s	871.669us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.520s	43.891us	1	1	100.00
	xbar_smoke_large_delays	39.780s	5916.344us	1	1	100.00
	xbar_smoke_slow_rsp	34.230s	3284.206us	1	1	100.00
	xbar_random_zero_delays	28.110s	435.034us	1	1	100.00
	xbar_random_large_delays	126.170s	19222.253us	1	1	100.00
	xbar_random_slow_rsp	204.350s	20301.100us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	25.140s	294.001us	1	1	100.00
	xbar_error_and_unmapped_addr	40.610s	1227.519us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	9.530s	127.180us	1	1	100.00
	xbar_error_and_unmapped_addr	40.610s	1227.519us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	8.190s	103.221us	1	1	100.00
	xbar_access_same_device_slow_rsp	245.880s	25616.457us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	10.190s	64.382us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	105.550s	3638.857us	1	1	100.00
	xbar_stress_all_with_error	353.080s	13113.430us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	197.200s	1768.089us	1	1	100.00
	xbar_stress_all_with_reset_error	93.830s	468.243us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3775.610s	15490.398us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	3675.420s	31655.618us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3957.300s	22881.906us	1	1	100.00
rom_e2e_boot_policy_valid				15	15	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	3028.280s	13054.751us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	3992.850s	16270.276us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	3947.540s	15478.358us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	3804.490s	15530.544us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	3854.370s	15121.571us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	2979.790s	11322.954us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	4200.260s	17226.920us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	3940.700s	15752.561us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	4059.340s	16760.532us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	4063.180s	16712.721us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	5428.480s	18704.280us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	6819.910s	24612.573us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	6667.160s	23972.501us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	6615.120s	24414.732us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	6561.920s	23581.109us	1	1	100.00
rom_e2e_sigverify_always				15	15	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	5461.010s	23238.433us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	6533.060s	31293.252us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	6772.770s	27788.250us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	6475.930s	26916.501us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	6346.300s	27523.151us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	2954.790s	15357.874us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	3925.990s	22222.469us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	4035.010s	22128.212us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	4071.170s	22348.702us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	3682.930s	17949.381us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	2919.820s	10519.318us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	3731.400s	22899.606us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	3793.150s	22483.675us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	3847.960s	22434.852us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	3777.760s	29337.652us	1	1	100.00
rom_e2e_asm_init				5	5	100.00
	rom_e2e_asm_init_test_unlocked0	2934.770s	13544.937us	1	1	100.00
	rom_e2e_asm_init_dev	3847.420s	15906.882us	1	1	100.00
	rom_e2e_asm_init_prod	4009.450s	18806.622us	1	1	100.00
	rom_e2e_asm_init_prod_end	4099.420s	16960.751us	1	1	100.00
	rom_e2e_asm_init_rma	3818.270s	15357.949us	1	1	100.00
rom_e2e_keymgr_dpe_init				3	3	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_meas	7738.080s	30471.260us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_no_meas	7620.710s	28372.989us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas	7282.940s	30595.898us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3937.680s	15950.685us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.186s	0.000us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.186s	0.000us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	258.430s	2744.176us	1	1	100.00
	chip_sw_aes_enc_jitter_en	185.030s	2909.980us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	164.720s	2471.789us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	203.110s	3214.810us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	2141.590s	13154.787us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	249.870s	2777.613us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	529.630s	4930.900us	1	1	100.00
chip_sw_all_escalation_resets				0	1	0.00
	chip_sw_all_escalation_resets	182.310s	2840.378us	0	1	0.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	521.300s	4447.840us	1	1	100.00
	chip_plic_all_irqs_10	399.790s	3441.734us	1	1	100.00
	chip_plic_all_irqs_20	502.220s	3829.084us	1	1	100.00
chip_sw_alert_handler_entropy				0	1	0.00
	chip_sw_alert_handler_entropy	241.330s	2372.107us	0	1	0.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1182.850s	10160.481us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	224.330s	2446.080us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	255.200s	2563.812us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	308.950s	3034.308us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1423.400s	8908.304us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1186.050s	7412.017us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	1055.140s	7996.804us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10738.070s	254672.175us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	360.350s	4163.757us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	445.610s	5189.343us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	360.350s	4163.757us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	655.260s	8113.954us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	655.260s	8113.954us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	353.590s	6859.775us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	414.960s	4817.705us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	824.800s	5897.045us	1	1	100.00
	chip_sw_aes_idle	203.110s	3214.810us	1	1	100.00
	chip_sw_hmac_enc_idle	239.920s	2503.727us	1	1	100.00
	chip_sw_kmac_idle	275.240s	3068.973us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	338.980s	3856.862us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	440.850s	4772.966us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	428.850s	3885.932us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	293.210s	3872.935us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	956.790s	9961.342us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	526.990s	4249.600us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	480.860s	5017.895us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	492.520s	3934.499us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	492.730s	4583.881us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	477.260s	3946.332us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	455.870s	4884.531us	1	1	100.00
	chip_sw_ast_clk_outputs	738.440s	7653.717us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	862.420s	14455.379us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	492.520s	3934.499us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	492.730s	4583.881us	1	1	100.00
chip_sw_clkmgr_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4303.730s	18700.676us	1	1	100.00
	chip_sw_aes_enc_jitter_en	185.030s	2909.980us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	788.120s	5780.516us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	231.380s	3307.339us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	2015.130s	11934.188us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	216.980s	2754.126us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	499.830s	4682.816us	1	1	100.00
	chip_sw_clkmgr_jitter	246.870s	2688.116us	1	1	100.00
chip_sw_clkmgr_extended_range				8	8	100.00
	chip_sw_clkmgr_jitter_reduced_freq	181.790s	2642.712us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4439.670s	26427.247us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	205.110s	3389.394us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	212.160s	3030.030us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1755.980s	12963.181us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	278.020s	3529.155us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	402.550s	4643.851us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	4000.200s	25390.537us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	738.440s	7653.717us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				0	1	0.00
	chip_sw_clkmgr_sleep_frequency	494.070s	4134.882us	0	1	0.00
chip_sw_clkmgr_reset_frequency				0	1	0.00
	chip_sw_clkmgr_reset_frequency	526.960s	8527.694us	0	1	0.00
chip_sw_clkmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	182.310s	2840.378us	0	1	0.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1423.400s	8908.304us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2812.990s	24287.040us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	353.290s	4117.702us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	918.370s	9463.032us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	193.050s	2534.798us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	2185.250s	11088.946us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	186.040s	2967.055us	1	1	100.00
	chip_sw_edn_entropy_reqs	1100.480s	7355.542us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	186.040s	2967.055us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2812.990s	24287.040us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	209.030s	2772.997us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	181.670s	2486.318us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	231.380s	3307.339us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	239.920s	2503.727us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1773.240s	10797.032us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	2301.830s	12010.380us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	544.860s	5052.967us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	577.830s	4892.508us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	501.490s	4610.162us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	351.570s	3684.857us	1	1	100.00
chip_sw_keymgr_dpe_key_derivation				2	2	100.00
	chip_sw_keymgr_dpe_key_derivation	881.540s	6517.430us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	2015.130s	11934.188us	1	1	100.00
chip_sw_keymgr_dpe_sideload_kmac				1	1	100.00
	chip_sw_keymgr_dpe_sideload_kmac	1764.550s	10629.123us	1	1	100.00
chip_sw_keymgr_dpe_sideload_aes				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	2141.590s	13154.787us	1	1	100.00
chip_sw_keymgr_dpe_sideload_otbn				0	1	0.00
	chip_sw_keymgr_dpe_sideload_otbn	3600.167s	0.000us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	242.330s	2722.976us	1	1	100.00
	chip_sw_kmac_mode_kmac	242.400s	2849.613us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	216.980s	2754.126us	1	1	100.00
chip_sw_kmac_app_keymgr_dpe				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	881.540s	6517.430us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	898.590s	14159.990us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	539.420s	9720.076us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1046.150s	6570.922us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	275.240s	3068.973us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	529.630s	4930.900us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	606.050s	8138.544us	1	1	100.00
	chip_tap_straps_rma	435.970s	6582.159us	1	1	100.00
	chip_tap_straps_prod	797.680s	9469.517us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	196.830s	2812.835us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	898.590s	14159.990us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	898.590s	14159.990us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	898.590s	14159.990us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_prod	1229.520s	8231.307us	1	1	100.00
chip_sw_lc_ctrl_broadcast				18	21	85.71
	chip_sw_rram_rma_unlocked	333.860s	10010.120us	0	1	0.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	340.440s	3660.306us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	646.190s	6337.979us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	692.650s	5754.511us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	791.310s	6693.154us	0	1	0.00
	chip_sw_lc_ctrl_transition	898.590s	14159.990us	1	1	100.00
	chip_sw_rram_ctrl_lc_rw_en	442.410s	4178.159us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	881.540s	6517.430us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	840.520s	15037.409us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	537.760s	6418.669us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	862.420s	14455.379us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	526.990s	4249.600us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	480.860s	5017.895us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	492.520s	3934.499us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	492.730s	4583.881us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	477.260s	3946.332us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	455.870s	4884.531us	1	1	100.00
	chip_tap_straps_dev	606.050s	8138.544us	1	1	100.00
	chip_tap_straps_rma	435.970s	6582.159us	1	1	100.00
	chip_tap_straps_prod	797.680s	9469.517us	1	1	100.00
	chip_rv_dm_lc_disabled	156.820s	4549.111us	0	1	0.00
chip_lc_scrap				1	4	25.00
	chip_sw_lc_ctrl_rma_to_scrap	403.820s	5680.508us	0	1	0.00
	chip_sw_lc_ctrl_raw_to_scrap	906.150s	26232.918us	0	1	0.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	444.880s	8214.870us	0	1	0.00
	chip_sw_lc_ctrl_rand_to_scrap	368.720s	5764.371us	1	1	100.00
chip_lc_test_locked				0	2	0.00
	chip_sw_lc_walkthrough_testunlocks	3311.550s	60000.000us	0	1	0.00
	chip_rv_dm_lc_disabled	156.820s	4549.111us	0	1	0.00
chip_sw_lc_walkthrough				1	5	20.00
	chip_sw_lc_walkthrough_dev	1775.440s	22888.491us	0	1	0.00
	chip_sw_lc_walkthrough_prod	1735.580s	17517.579us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	1487.100s	20302.130us	1	1	100.00
	chip_sw_lc_walkthrough_rma	965.590s	13344.803us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	3311.550s	60000.000us	0	1	0.00
chip_sw_lc_ctrl_volatile_raw_unlock				3	3	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock	284.110s	5439.700us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	215.470s	4404.466us	1	1	100.00
	rom_volatile_raw_unlock	308.170s	5583.510us	1	1	100.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	4191.680s	16853.618us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4303.730s	18700.676us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	824.800s	5897.045us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	824.800s	5897.045us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	824.800s	5897.045us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	460.750s	3920.055us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	898.590s	14159.990us	1	1	100.00
chip_sw_otp_ctrl_keys				3	4	75.00
	chip_sw_otbn_mem_scramble	460.750s	3920.055us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	881.540s	6517.430us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	390.280s	4432.700us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3445.040s	60000.000us	0	1	0.00
chip_sw_otp_ctrl_entropy				3	4	75.00
	chip_sw_otbn_mem_scramble	460.750s	3920.055us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	881.540s	6517.430us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	390.280s	4432.700us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3445.040s	60000.000us	0	1	0.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	898.590s	14159.990us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	551.230s	5987.158us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	196.830s	2812.835us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				4	5	80.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	340.440s	3660.306us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	646.190s	6337.979us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	692.650s	5754.511us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	791.310s	6693.154us	0	1	0.00
	chip_sw_lc_ctrl_transition	898.590s	14159.990us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	991.710s	6822.720us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	405.640s	7625.721us	1	1	100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	172.900s	3334.038us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	228.160s	3280.702us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	555.670s	7746.919us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_por_reset	386.800s	4109.795us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1149.630s	22962.916us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				1	2	50.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	245.940s	5091.661us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	655.260s	8113.954us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	253.810s	3445.904us	0	1	0.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	430.910s	3945.237us	1	1	100.00
chip_sw_pwrmgr_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	405.640s	7625.721us	1	1	100.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	342.770s	3987.269us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	604.200s	8836.033us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	334.710s	6453.704us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	188.540s	3111.077us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	473.630s	7882.230us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	752.200s	6868.831us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	989.180s	9245.307us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1535.400s	20816.409us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	259.430s	3025.305us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	182.310s	2840.378us	0	1	0.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	840.520s	15037.409us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	840.520s	15037.409us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	989.180s	9245.307us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	473.630s	7882.230us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	430.910s	3945.237us	1	1	100.00
	chip_sw_pwrmgr_smoketest	445.610s	5189.343us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	328.720s	3954.150us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	443.510s	5500.416us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	287.150s	3725.977us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1182.850s	10160.481us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	185.700s	2227.033us	1	1	100.00
chip_sw_rstmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	182.310s	2840.378us	0	1	0.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1186.050s	7412.017us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	611.620s	4339.103us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	607.310s	4462.597us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	207.150s	3081.005us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				0	1	0.00
	chip_sw_rv_core_ibex_icache_invalidate	3445.040s	60000.000us	0	1	0.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	443.510s	5500.416us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	443.510s	5500.416us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	183.130s	2894.759us	1	1	100.00
chip_jtag_csr_rw				0	1	0.00
	chip_jtag_csr_rw	116.450s	2140.808us	0	1	0.00
chip_jtag_mem_access				0	1	0.00
	chip_jtag_mem_access	85.900s	2260.725us	0	1	0.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	328.720s	3954.150us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	266.080s	2996.099us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	172.810s	3077.423us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	435.970s	6582.159us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	156.820s	4549.111us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	521.300s	4447.840us	1	1	100.00
	chip_plic_all_irqs_10	399.790s	3441.734us	1	1	100.00
	chip_plic_all_irqs_20	502.220s	3829.084us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	250.710s	2772.376us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	258.720s	3141.499us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3775.610s	15490.398us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	519.840s	5875.954us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	349.370s	3270.661us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	299.310s	2842.473us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	318.350s	3199.475us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	390.280s	4432.700us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	499.830s	4682.816us	1	1	100.00
chip_sw_sleep_sram_ret_contents				0	2	0.00
	chip_sw_sleep_sram_ret_contents_no_scramble	281.640s	3422.565us	0	1	0.00
	chip_sw_sleep_sram_ret_contents_scramble	262.010s	2764.874us	0	1	0.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	537.760s	6418.669us	1	1	100.00
chip_sw_sram_lc_escalation				1	2	50.00
	chip_sw_all_escalation_resets	182.310s	2840.378us	0	1	0.00
	chip_sw_data_integrity_escalation	610.000s	6164.372us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	752.200s	6868.831us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1163.650s	21962.051us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	244.300s	2776.957us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	308.840s	3182.781us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	394.100s	4158.728us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1163.650s	21962.051us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1163.650s	21962.051us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	3089.590s	20270.016us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	3089.590s	20270.016us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	358.850s	5698.545us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.186s	0.000us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	171.850s	2850.082us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	217.300s	2822.532us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	372.410s	3676.358us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	362.420s	3581.932us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	979.110s	8001.783us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	6300.850s	31724.566us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	2174.850s	11949.436us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	192.550s	2973.672us	1	1	100.00

V2S

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	296.200s	2716.708us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				0	1	0.00
	chip_sw_rv_core_ibex_lockstep_glitch	177.000s	2790.123us	0	1	0.00

14/24 passed

58.33 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	12698.770s	72537.904us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1480.590s	6531.191us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	118.530s	2038.543us	0	1	0.00
	rom_e2e_jtag_debug_dev	97.800s	2479.849us	0	1	0.00
	rom_e2e_jtag_debug_rma	101.120s	2016.648us	0	1	0.00
rom_e2e_jtag_inject				1	3	33.33
	rom_e2e_jtag_inject_test_unlocked0	84.120s	2290.604us	0	1	0.00
	rom_e2e_jtag_inject_dev	92.060s	2320.411us	0	1	0.00
	rom_e2e_jtag_inject_rma	258.080s	4248.063us	1	1	100.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	271.122s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	372.650s	3210.072us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	384.540s	2638.586us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	1233.570s	5758.033us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1804.810s	10181.964us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	312.560s	2032.433us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	251.870s	3172.920us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	336.160s	4730.181us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	481.730s	4773.129us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	989.180s	9245.307us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	118.530s	2038.543us	0	1	0.00
	rom_e2e_jtag_debug_dev	97.800s	2479.849us	0	1	0.00
	rom_e2e_jtag_debug_rma	101.120s	2016.648us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	373.210s	4072.024us	1	1	100.00
chip_sw_plic_alerts				0	1	0.00
	chip_sw_all_escalation_resets	182.310s	2840.378us	0	1	0.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	6460.070s	38082.701us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	6460.070s	38082.701us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				0	1	0.00
	chip_sw_spi_device_pinmux_sleep_retention	246.430s	2815.352us	0	1	0.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	488.750s	3862.415us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3828.080s	18982.533us	1	1	100.00

unmapped

1/8 passed

12.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	8	12.50
	chip_sw_rstmgr_rst_cnsty_escalation	54.120s	10.340us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	115.220s	2614.121us	0	1	0.00
	chip_sw_otp_ctrl_descrambling	285.340s	3203.764us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	207.830s	2859.591us	0	1	0.00
	chip_sw_pwrmgr_sleep_wake_5_bug	10.214s	0.000us	0	1	0.00
	ate_bootstrap_flash_erase	820.120s	10010.160us	0	1	0.00
	ate_bootstrap_one_frame	10800.142s	0.000us	0	1	0.00
	ate_bootstrap_disjoint	10800.154s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error				15 test runs
	chip_sw_sleep_pin_wake	115604131121930566182416249534974025923006381462632205236357378261897212711949	381	UVM_INFO @ 2495.762572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_pin_retention	94669783671883837224340815661885875619443654606202008837579477148791892749543	378	UVM_INFO @ 2838.223416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_spi_device_pinmux_sleep_retention	56711955274567843872312848175173519044175368018924443250391261262663896731507	373	UVM_INFO @ 2815.351800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	89638936440738230968712247454151127177920633955466447192357970816994792358015	391	UVM_INFO @ 7882.230220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	96300692537688281940887204253183117351484258814925258446595800209380951895585	376	UVM_INFO @ 3445.903768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_por_reset	70174914272334134032573016209259543805192944404718122092897462494888280715777	387	UVM_INFO @ 4109.794891 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	109123142738073459579741729908899493220941199384941870518684192728549519685732	405	UVM_INFO @ 8836.032504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_no_scramble	14001395622036093460405940975013845811647590728370618056373748860995358983415	376	UVM_INFO @ 3422.564504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_scramble	73559264325039682128814199539025124576054460424517207578543815947230026067848	380	UVM_INFO @ 2764.874364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	63089782646365569915738836254209783047413299538937396457769828582496580296552	371	UVM_INFO @ 2796.430560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_clkmgr_sleep_frequency	97461010749335780346089022980432439690929643668822264451067478060806473180918	406	UVM_INFO @ 4134.881510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	39922265933391600735492514774520168106958418496766580504815754655645387693835	373	UVM_INFO @ 3280.702296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_lowpower_cancel	110660242981716663620661492005893890947734979739947448712369666198755930953374	371	UVM_INFO @ 2859.590764 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_wake_ups	101944172206996278581778657831017558771374945848482818090401207025010736963033	372	UVM_INFO @ 3334.037576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_dm_access_after_wakeup	27022629733060100319472755375802432242169751881659714071780836912284430979030	383	UVM_INFO @ 3077.423400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				5 test runs
	chip_sw_exit_test_unlocked_bootstrap	33927358005777691587667138073402150762662516961179358120240532090787494953567	None
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	56165936399596111731074460412264931184525189156229686372568257974982274469999	None
	chip_sw_keymgr_dpe_sideload_otbn	72718524175060085039062589055702609395207126473812493417631743541505962732499	None
	ate_bootstrap_one_frame	71783281184189530611212544443416730770746700059245578732433684004318676370624	None
	ate_bootstrap_disjoint	48458278286831533620531593960856065776739254373491051649337632432504021969101	None
Error-[NOA] Null object access				4 test runs
	chip_sw_otp_ctrl_rot_auth_config	19407686941870087185823462528426468412691605704684849472429569145576456255033	372	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	111548507597441877862837930986007798076836851552874944951980494947811298905081	396	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	43456914382771398970690195346348438872991649253310133968910348600208529973238	372	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	17158902064751614911545884299987687504831388164532563130648261637285367660321	372	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	885874438438648827965874952505333394651930027628679635430109662295369181711	432	UVM_INFO @ 22888.491160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	68051261922385626802904239298875625585852936078355591501986680665309751735172	432	UVM_INFO @ 17517.578595 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	95479255560993049896696708542041335023746021978599539781052165488280507201245	404	UVM_INFO @ 13344.803260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [] vs [*])				3 test runs
	rom_e2e_jtag_debug_test_unlocked0	96271374661398599302490003639031409750686446312499817264434450948668180614967	352	UVM_INFO @ 2038.542500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_dev	34876777781370029127314533784906927894324021855871207459559446232350167748784	352	UVM_INFO @ 2479.849500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_rma	88639927106102373139366560675110937529524134973414261269290240968418685144898	352	UVM_INFO @ 2016.648000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl				2 test runs
	chip_sw_lc_ctrl_rma_to_scrap	75821867636361692200780224034477911698498189858971061189155608534135075984594	376	UVM_INFO @ 5680.507612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_ctrl_test_locked0_to_scrap	77835875507571038000022572957673876814379394194326580460476524137646499454192	374	UVM_INFO @ 8214.869885 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue				2 test runs
	chip_sw_lc_walkthrough_testunlocks	93771044368098079196736723839730976382511022824599097093244364084166544175180	531	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_core_ibex_icache_invalidate	35181325719090402154512785838680576146600155854012321080812442289024559195690	376	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error				2 test runs
	chip_sw_alert_handler_lpg_sleep_mode_pings	80650578754139781843723832987493581890295181083971092683036759991065951415889	372	UVM_INFO @ 3034.307864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_alert_handler_entropy	92441194315679607294918298079135212780819667043397221885857017695163085623498	450	UVM_INFO @ 2372.107192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts!				2 test runs
	chip_jtag_csr_rw	107859783121507207989586259614506937574982239592661748025013946805532710311072	5364	UVM_INFO @ 2140.807960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_jtag_mem_access	54969576439775214786849039834557995370763022363538003020719793770069861988201	5364	UVM_INFO @ 2260.724806 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	19940018838615090399755498541950280393127391518013557198702760674977831244453	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	32161907798937983660944765069919384556752719595130299962915700244534433821565	None	Another command (pid=802916) is running. Waiting for it to complete on the server (server_pid=202165)... Another command (pid=801175) is running. Waiting for it to complete on the server (server_pid=202165)... Another command (pid=758933) is running. Waiting for it to complete on the server (server_pid=202165)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert fatal triggered unexpectedly				1 test run
	chip_same_csr_outstanding	29678643285432593218681934889126600212863453421452443082183132082300358098430	281	UVM_INFO @ 4864.330800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1072)] Unexpected fault				1 test run
	chip_sw_all_escalation_resets	62909483740693900531993850380344969437677098322841917598701939618304047704843	374	UVM_INFO @ 2840.377982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	73427010436005789425899173369727960475504301639627784922813536611360256858609	364	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	20689163738096847369533249066114867672581181896035642781392865961977136912037	390	UVM_INFO @ 3270.661213 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred!				1 test run
	chip_sw_rram_rma_unlocked	106079558687508504961342872302173639775254436618378612329218810066528818446713	336	UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	78109173828782634410111106235395423472228189422751522759649979899313759817965	403	UVM_INFO @ 6693.154168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	80236328832428693834008872262577667443945554687893297010430555903779164366751	379	UVM_ERROR @ 3172.920320 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3172.920320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_ctrl_raw_to_scrap	15132245794288654010611117561566215065700950580338865507495078238519310236850	365	UVM_INFO @ 26232.918477 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				1 test run
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	43388192153523921847343084733594740610731850790297568520938099452238257965241	377	UVM_ERROR @ 5091.661000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 5091.661000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	53448939508400004792851836051120757314793985110808134075647882248266522829302	376	UVM_ERROR @ 3111.077400 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3111.077400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:385)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	94009946430154801474755407873940995524127644211263653077772281924025431002652	370	UVM_INFO @ 2777.612670 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	82577980232000024593511101512420074176916695913965886097602819396547270829600	372	UVM_INFO @ 2563.811760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_hmac_multistream	75303653619470268093740269547129516720633413000474525412008249391678219033895	448	UVM_INFO @ 12010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.				1 test run
	chip_sw_clkmgr_reset_frequency	3240708060797219021128443128031370602340007643249931857384408282730176770993	399	UVM_INFO @ 8527.694150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	18652940541959434996478942081435664777700438355775365778635775942184055793415	406	UVM_INFO @ 3210.072064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:664) [chip_rv_dm_lc_disabled_vseq] Check failed rsp.d_error == exp_err_rsp (* [] vs []) unexpected error response for addr:				1 test run
	chip_rv_dm_lc_disabled	4983020517922396941434735640926956962288999286124478942716650369407237014388	299	UVM_INFO @ 4549.110720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [] vs [*]) Major alert did not match expectation.				1 test run
	chip_sw_rv_core_ibex_lockstep_glitch	9642650355064228340498671779727947039431241773259827889751615246788890545358	390	UVM_INFO @ 2790.122984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	106512656548342197379879307426329192681479164891159097048476956645821554399947	390	UVM_INFO @ 9229.354803 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	57013371858935546268265819021385366861179634046270414657926033496683571833765	338	UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---