Simulation Results: clkmgr

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 91.27 %
  • code
  • 97.16 %
  • assert
  • 92.94 %
  • func
  • 83.70 %
  • line
  • 98.62 %
  • branch
  • 98.02 %
  • cond
  • 89.96 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.430s 84.431us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.090s 28.566us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.430s 108.545us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 7.600s 1195.671us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.950s 100.703us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.450s 32.300us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.430s 108.545us 1 1 100.00
clkmgr_csr_aliasing 1.950s 100.703us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.990s 25.049us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.120s 36.519us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.390s 78.866us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.800s 17.182us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.430s 84.431us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 9.280s 1898.044us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.520s 663.284us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 9.280s 1898.044us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 13.830s 4297.591us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.120s 56.441us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.800s 49.388us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.800s 49.388us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.090s 28.566us 1 1 100.00
clkmgr_csr_rw 1.430s 108.545us 1 1 100.00
clkmgr_csr_aliasing 1.950s 100.703us 1 1 100.00
clkmgr_same_csr_outstanding 1.880s 224.983us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.090s 28.566us 1 1 100.00
clkmgr_csr_rw 1.430s 108.545us 1 1 100.00
clkmgr_csr_aliasing 1.950s 100.703us 1 1 100.00
clkmgr_same_csr_outstanding 1.880s 224.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.940s 2.055us 0 1 0.00
clkmgr_tl_intg_err 5.650s 831.725us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 641.200s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 641.200s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 641.200s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 641.200s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 496.480s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 5.650s 831.725us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 9.280s 1898.044us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.520s 663.284us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 641.200s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.250s 27.981us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.260s 39.721us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.970s 16.558us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.270s 66.451us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.050s 20.799us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.430s 108.545us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.940s 2.055us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.430s 108.545us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.430s 108.545us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.940s 2.055us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.410s 655.512us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 222.200s 54417.006us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
clkmgr_shadow_reg_errors 35795744954359997486911922317711204551700959524466908491553537434314664697944 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 7421555050617147702648180080483890966818539598135169992423536958906417653242 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 68407239958286458736734394688374176887697973323323167130679709732041105988560 84
UVM_INFO @ 2054784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---