Simulation Results: edn/edn0

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 86.56 %
  • code
  • 82.10 %
  • assert
  • 97.61 %
  • func
  • 79.96 %
  • line
  • 97.77 %
  • branch
  • 92.33 %
  • cond
  • 87.46 %
  • toggle
  • 81.35 %
  • FSM
  • 51.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.340s 26.994us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.270s 17.967us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.250s 14.434us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.270s 188.537us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.630s 80.363us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.340s 19.985us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.250s 14.434us 1 1 100.00
edn_csr_aliasing 1.630s 80.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.580s 47.039us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.580s 47.039us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.580s 47.039us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.460s 25.337us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.600s 71.034us 1 1 100.00
errs 1 1 100.00
edn_err 1.230s 37.685us 1 1 100.00
disable 2 2 100.00
edn_disable 1.240s 20.756us 1 1 100.00
edn_disable_auto_req_mode 1.610s 50.472us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.090s 334.021us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.210s 25.462us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.520s 24.918us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.870s 224.797us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.870s 224.797us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.270s 17.967us 1 1 100.00
edn_csr_rw 1.250s 14.434us 1 1 100.00
edn_csr_aliasing 1.630s 80.363us 1 1 100.00
edn_same_csr_outstanding 1.290s 34.203us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.270s 17.967us 1 1 100.00
edn_csr_rw 1.250s 14.434us 1 1 100.00
edn_csr_aliasing 1.630s 80.363us 1 1 100.00
edn_same_csr_outstanding 1.290s 34.203us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 11.730s 2216.743us 1 1 100.00
edn_tl_intg_err 2.120s 90.414us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.300s 51.453us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.600s 71.034us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 11.730s 2216.743us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 11.730s 2216.743us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 11.730s 2216.743us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 11.730s 2216.743us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.600s 71.034us 1 1 100.00
edn_sec_cm 11.730s 2216.743us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.600s 71.034us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.120s 90.414us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 96.140s 7781.099us 1 1 100.00