Simulation Results: edn/edn1

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 87.59 %
  • code
  • 83.92 %
  • assert
  • 98.18 %
  • func
  • 80.67 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 90.15 %
  • toggle
  • 95.70 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.250s 198.678us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.210s 16.340us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.090s 21.177us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.610s 175.829us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.510s 88.209us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.570s 43.816us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.090s 21.177us 1 1 100.00
edn_csr_aliasing 1.510s 88.209us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.630s 36.130us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.630s 36.130us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.630s 36.130us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.270s 28.878us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.650s 30.020us 1 1 100.00
errs 1 1 100.00
edn_err 1.090s 33.357us 1 1 100.00
disable 2 2 100.00
edn_disable 1.080s 40.477us 1 1 100.00
edn_disable_auto_req_mode 1.230s 167.000us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.380s 43.132us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.040s 76.355us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.120s 195.266us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.020s 112.615us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.020s 112.615us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.210s 16.340us 1 1 100.00
edn_csr_rw 1.090s 21.177us 1 1 100.00
edn_csr_aliasing 1.510s 88.209us 1 1 100.00
edn_same_csr_outstanding 1.380s 35.319us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.210s 16.340us 1 1 100.00
edn_csr_rw 1.090s 21.177us 1 1 100.00
edn_csr_aliasing 1.510s 88.209us 1 1 100.00
edn_same_csr_outstanding 1.380s 35.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.780s 654.056us 1 1 100.00
edn_tl_intg_err 1.890s 396.990us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.230s 15.811us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.650s 30.020us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.780s 654.056us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.780s 654.056us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.780s 654.056us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.780s 654.056us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.650s 30.020us 1 1 100.00
edn_sec_cm 3.780s 654.056us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.650s 30.020us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.890s 396.990us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 54.980s 6352.537us 1 1 100.00