Simulation Results: hmac

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 76.07 %
  • code
  • 86.71 %
  • assert
  • 97.60 %
  • func
  • 43.91 %
  • line
  • 99.54 %
  • branch
  • 98.54 %
  • cond
  • 95.18 %
  • toggle
  • 46.17 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 5.010s 518.602us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.170s 23.198us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.240s 115.181us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 16.460s 3693.543us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.490s 401.922us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.780s 56.631us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.240s 115.181us 1 1 100.00
hmac_csr_aliasing 6.490s 401.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 10.400s 3427.450us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 120.530s 13482.644us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 192.040s 30160.627us 1 1 100.00
hmac_test_sha384_vectors 410.420s 73952.439us 1 1 100.00
hmac_test_sha512_vectors 32.140s 2237.813us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 247.897us 1 1 100.00
hmac_test_hmac384_vectors 9.570s 533.972us 1 1 100.00
hmac_test_hmac512_vectors 12.630s 2966.706us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 25.550s 2576.901us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 1226.790s 10803.303us 1 1 100.00
error 1 1 100.00
hmac_error 4.870s 1428.456us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 135.710s 54066.493us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 5.010s 518.602us 1 1 100.00
hmac_long_msg 10.400s 3427.450us 1 1 100.00
hmac_back_pressure 120.530s 13482.644us 1 1 100.00
hmac_datapath_stress 1226.790s 10803.303us 1 1 100.00
hmac_burst_wr 25.550s 2576.901us 1 1 100.00
hmac_stress_all 572.580s 32827.143us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 5.010s 518.602us 1 1 100.00
hmac_long_msg 10.400s 3427.450us 1 1 100.00
hmac_back_pressure 120.530s 13482.644us 1 1 100.00
hmac_datapath_stress 1226.790s 10803.303us 1 1 100.00
hmac_wipe_secret 135.710s 54066.493us 1 1 100.00
hmac_test_sha256_vectors 192.040s 30160.627us 1 1 100.00
hmac_test_sha384_vectors 410.420s 73952.439us 1 1 100.00
hmac_test_sha512_vectors 32.140s 2237.813us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 247.897us 1 1 100.00
hmac_test_hmac384_vectors 9.570s 533.972us 1 1 100.00
hmac_test_hmac512_vectors 12.630s 2966.706us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 5.010s 518.602us 1 1 100.00
hmac_long_msg 10.400s 3427.450us 1 1 100.00
hmac_back_pressure 120.530s 13482.644us 1 1 100.00
hmac_datapath_stress 1226.790s 10803.303us 1 1 100.00
hmac_burst_wr 25.550s 2576.901us 1 1 100.00
hmac_error 4.870s 1428.456us 1 1 100.00
hmac_wipe_secret 135.710s 54066.493us 1 1 100.00
hmac_test_sha256_vectors 192.040s 30160.627us 1 1 100.00
hmac_test_sha384_vectors 410.420s 73952.439us 1 1 100.00
hmac_test_sha512_vectors 32.140s 2237.813us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 247.897us 1 1 100.00
hmac_test_hmac384_vectors 9.570s 533.972us 1 1 100.00
hmac_test_hmac512_vectors 12.630s 2966.706us 1 1 100.00
hmac_stress_all 572.580s 32827.143us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 572.580s 32827.143us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.830s 17.455us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.770s 33.598us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.180s 258.645us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.180s 258.645us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.170s 23.198us 1 1 100.00
hmac_csr_rw 1.240s 115.181us 1 1 100.00
hmac_csr_aliasing 6.490s 401.922us 1 1 100.00
hmac_same_csr_outstanding 2.470s 158.962us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.170s 23.198us 1 1 100.00
hmac_csr_rw 1.240s 115.181us 1 1 100.00
hmac_csr_aliasing 6.490s 401.922us 1 1 100.00
hmac_same_csr_outstanding 2.470s 158.962us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.310s 171.941us 1 1 100.00
hmac_tl_intg_err 3.610s 593.428us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.610s 593.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 5.010s 518.602us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.190s 84.726us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 2.800s 140.959us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.330s 286.694us 1 1 100.00