Simulation Results

Simulation Results: i2c

25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
86.56 %

code
79.02 %

assert
96.19 %

func
84.46 %

line
96.63 %

branch
92.90 %

cond
87.49 %

toggle
74.04 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		92.68%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	57.730s	3614.002us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	14.120s	5000.672us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.990s	52.993us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.920s	48.995us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.400s	814.591us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.540s	49.995us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.090s	181.448us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.920s	48.995us	1	1	100.00
	i2c_csr_aliasing	1.540s	49.995us	1	1	100.00

38/41 passed

92.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.150s	879.956us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	260.240s	50195.234us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	141.750s	5930.597us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.010s	22.168us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	91.450s	17061.515us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	62.170s	2575.520us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.410s	131.538us	1	1	100.00
	i2c_host_fifo_fmt_empty	5.130s	1125.231us	1	1	100.00
	i2c_host_fifo_reset_rx	3.570s	273.597us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	104.930s	9792.962us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	31.060s	3005.618us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.240s	475.503us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.890s	409.020us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	43.760s	14792.690us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	7.710s	1136.838us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	24.940s	2959.187us	1	1	100.00
	i2c_target_intr_smoke	7.420s	1389.116us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.760s	623.911us	1	1	100.00
	i2c_target_fifo_reset_tx	1.380s	596.549us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	1508.090s	66996.417us	1	1	100.00
	i2c_target_stress_rd	24.940s	2959.187us	1	1	100.00
	i2c_target_intr_stress_wr	259.240s	21536.757us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.090s	7442.224us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	9.980s	2582.656us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.860s	794.768us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	3.090s	401.598us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.540s	429.903us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.280s	140.279us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	141.750s	5930.597us	1	1	100.00
	i2c_host_perf_precise	1.590s	46.227us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	31.060s	3005.618us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.730s	117.719us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	3.480s	552.433us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.170s	1881.886us	1	1	100.00
	i2c_target_nack_txstretch	1.790s	286.433us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	5.130s	330.444us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	2.230s	3684.150us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.900s	24.800us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.950s	22.282us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.060s	142.199us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.060s	142.199us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.990s	52.993us	1	1	100.00
	i2c_csr_rw	0.920s	48.995us	1	1	100.00
	i2c_csr_aliasing	1.540s	49.995us	1	1	100.00
	i2c_same_csr_outstanding	1.410s	56.345us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.990s	52.993us	1	1	100.00
	i2c_csr_rw	0.920s	48.995us	1	1	100.00
	i2c_csr_aliasing	1.540s	49.995us	1	1	100.00
	i2c_same_csr_outstanding	1.410s	56.345us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.500s	103.028us	1	1	100.00
	i2c_sec_cm	1.300s	66.456us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.500s	103.028us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	12.060s	6017.375us	1
target_error_intr				1
	i2c_target_unexp_stop	1.780s	311.878us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	7.550s	1694.322us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	92653556711903167269773322220154861105211560375404148658750289141863501374265	118	UVM_INFO @ 879955960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	27557257222067269272454442810401503030484846023018719100513662739989158852383	98	UVM_INFO @ 1694322314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	55475959189940646984432427169671881886648266654837026973709340398457336768352	90	UVM_INFO @ 409020181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'				1 test run
	i2c_target_unexp_stop	13527733335600314896732982087365793325300899533093479212411586241243645656725	85	UVM_ERROR @ 311877893 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 311877893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	47350125761116061739604725646176264234826643269310391751597162935398957015137	107	UVM_INFO @ 6017375213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:714) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_mode_toggle	20337316102783005075835593045362265849013798986039738835772251847087201643805	91	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @8293