Simulation Results: keymgr_dpe/earlgrey

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 65.19 %
  • code
  • 82.67 %
  • assert
  • 97.67 %
  • func
  • 15.22 %
  • line
  • 97.60 %
  • branch
  • 93.77 %
  • cond
  • 86.84 %
  • toggle
  • 59.47 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_dpe_smoke 15.100s 3439.835us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 1.320s 100.793us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 1.040s 17.344us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 6.960s 520.004us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 2.920s 535.334us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.180s 29.813us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 1.040s 17.344us 1 1 100.00
keymgr_dpe_csr_aliasing 2.920s 535.334us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 0.950s 30.194us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 1.180s 58.306us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 3.550s 587.580us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 3.550s 587.580us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.320s 100.793us 1 1 100.00
keymgr_dpe_csr_rw 1.040s 17.344us 1 1 100.00
keymgr_dpe_csr_aliasing 2.920s 535.334us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.020s 90.043us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.320s 100.793us 1 1 100.00
keymgr_dpe_csr_rw 1.040s 17.344us 1 1 100.00
keymgr_dpe_csr_aliasing 2.920s 535.334us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.020s 90.043us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 6.150s 1183.601us 1 1 100.00
keymgr_dpe_tl_intg_err 4.930s 448.622us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.900s 4.810us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.900s 4.810us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.900s 4.810us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.900s 4.810us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 2.120s 54.266us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 6.150s 1183.601us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 6.150s 1183.601us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(reg2hw.control_shadowed.slot_src_sel.q < NumInstHwSlot)' 2 test runs
keymgr_dpe_shadow_reg_errors 33213192211559828490908337930988891203244435968458973067978268168226175896579 83
UVM_ERROR @ 4810023 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 4810023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_dpe_shadow_reg_errors_with_csr_rw 25326486050181670864104612288949518907245658848555405351558668639163746859510 83
UVM_ERROR @ 54266306 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 54266306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---