Simulation Results: lc_ctrl/volatile_unlock_disabled

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.21 %
  • code
  • 84.01 %
  • assert
  • 94.69 %
  • func
  • 91.94 %
  • line
  • 97.15 %
  • branch
  • 93.61 %
  • cond
  • 79.45 %
  • toggle
  • 86.29 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.350s 51.710us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.140s 47.012us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.120s 17.007us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.890s 68.771us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 70.894us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.770s 89.638us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.120s 17.007us 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 70.894us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.870s 308.429us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.810s 2982.811us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.080s 41.609us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.630s 340.962us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.260s 316.438us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.070s 932.252us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.260s 316.438us 1 1 100.00
lc_ctrl_prog_failure 2.630s 340.962us 1 1 100.00
lc_ctrl_errors 4.070s 932.252us 1 1 100.00
lc_ctrl_security_escalation 3.700s 1148.274us 1 1 100.00
lc_ctrl_jtag_state_failure 17.560s 2575.895us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.390s 2374.059us 1 1 100.00
lc_ctrl_jtag_errors 18.990s 1566.755us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.770s 1282.185us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.540s 411.735us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.390s 2374.059us 1 1 100.00
lc_ctrl_jtag_errors 18.990s 1566.755us 1 1 100.00
lc_ctrl_jtag_access 1.390s 144.133us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.960s 2373.021us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.820s 336.497us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.720s 64.391us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.070s 1062.855us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.830s 291.875us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.320s 193.568us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.140s 564.537us 1 1 100.00
lc_ctrl_jtag_alert_test 1.110s 60.554us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.570s 153.606us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.770s 199.877us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 64.380s 18650.307us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.110s 74.237us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.790s 424.917us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.790s 424.917us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.140s 47.012us 1 1 100.00
lc_ctrl_csr_rw 1.120s 17.007us 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 70.894us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.260s 52.281us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.140s 47.012us 1 1 100.00
lc_ctrl_csr_rw 1.120s 17.007us 1 1 100.00
lc_ctrl_csr_aliasing 1.450s 70.894us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.260s 52.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.250s 517.477us 1 1 100.00
lc_ctrl_tl_intg_err 1.650s 64.456us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.650s 64.456us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.810s 2982.811us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.260s 316.438us 1 1 100.00
lc_ctrl_sec_cm 7.250s 517.477us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.260s 316.438us 1 1 100.00
lc_ctrl_sec_cm 7.250s 517.477us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.260s 316.438us 1 1 100.00
lc_ctrl_sec_cm 7.250s 517.477us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.260s 316.438us 1 1 100.00
lc_ctrl_sec_cm 7.250s 517.477us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.260s 316.438us 1 1 100.00
lc_ctrl_sec_cm 7.250s 517.477us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.260s 316.438us 1 1 100.00
lc_ctrl_sec_cm 7.250s 517.477us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.260s 316.438us 1 1 100.00
lc_ctrl_sec_cm 7.250s 517.477us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.260s 316.438us 1 1 100.00
lc_ctrl_sec_cm 7.250s 517.477us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.700s 1148.274us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.870s 308.429us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.540s 411.735us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.510s 499.066us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.510s 499.066us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.270s 450.519us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.380s 1558.472us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.380s 1558.472us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 1.610s 107.867us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 11101276172385483788879301739962775357706717094739365709666859722206336591796 169
UVM_INFO @ 107867468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---