Simulation Results: lc_ctrl/volatile_unlock_enabled

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.47 %
  • code
  • 84.12 %
  • assert
  • 94.83 %
  • func
  • 92.47 %
  • line
  • 97.17 %
  • branch
  • 93.71 %
  • cond
  • 79.56 %
  • toggle
  • 87.53 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.010s 34.463us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.890s 327.022us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.730s 17.228us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.350s 37.155us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 76.912us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.840s 55.429us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.730s 17.228us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 76.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.580s 237.115us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.160s 842.549us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.900s 24.981us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.930s 113.024us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.470s 586.558us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.530s 375.191us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.470s 586.558us 1 1 100.00
lc_ctrl_prog_failure 1.930s 113.024us 1 1 100.00
lc_ctrl_errors 4.530s 375.191us 1 1 100.00
lc_ctrl_security_escalation 5.280s 1834.653us 1 1 100.00
lc_ctrl_jtag_state_failure 21.400s 1834.177us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.320s 1359.728us 1 1 100.00
lc_ctrl_jtag_errors 17.580s 6527.926us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.980s 671.102us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.150s 283.412us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.320s 1359.728us 1 1 100.00
lc_ctrl_jtag_errors 17.580s 6527.926us 1 1 100.00
lc_ctrl_jtag_access 2.110s 173.490us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.140s 1174.592us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.580s 132.209us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.340s 141.404us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.990s 798.351us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.610s 498.492us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.140s 84.779us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.560s 271.392us 1 1 100.00
lc_ctrl_jtag_alert_test 1.010s 67.656us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 9.170s 1241.606us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.780s 43.125us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 62.440s 48242.864us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.920s 500.548us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.750s 80.018us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.750s 80.018us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.890s 327.022us 1 1 100.00
lc_ctrl_csr_rw 0.730s 17.228us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 76.912us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.940s 49.208us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.890s 327.022us 1 1 100.00
lc_ctrl_csr_rw 0.730s 17.228us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 76.912us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.940s 49.208us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.980s 117.405us 1 1 100.00
lc_ctrl_tl_intg_err 1.840s 125.182us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.840s 125.182us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.160s 842.549us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.470s 586.558us 1 1 100.00
lc_ctrl_sec_cm 4.980s 117.405us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.470s 586.558us 1 1 100.00
lc_ctrl_sec_cm 4.980s 117.405us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.470s 586.558us 1 1 100.00
lc_ctrl_sec_cm 4.980s 117.405us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.470s 586.558us 1 1 100.00
lc_ctrl_sec_cm 4.980s 117.405us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.470s 586.558us 1 1 100.00
lc_ctrl_sec_cm 4.980s 117.405us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.470s 586.558us 1 1 100.00
lc_ctrl_sec_cm 4.980s 117.405us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.470s 586.558us 1 1 100.00
lc_ctrl_sec_cm 4.980s 117.405us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.470s 586.558us 1 1 100.00
lc_ctrl_sec_cm 4.980s 117.405us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.280s 1834.653us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 1.580s 237.115us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.150s 283.412us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.710s 426.756us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.710s 426.756us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.630s 2194.468us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.210s 366.939us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.210s 366.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 46.870s 8123.640us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 30272059728681146833758439843861245833502273608088989188256506166537541205403 8601
UVM_INFO @ 8123639541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---