Simulation Results: otbn

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.46 %
  • code
  • 86.25 %
  • assert
  • 90.26 %
  • func
  • 97.88 %
  • block
  • 99.27 %
  • line
  • 99.46 %
  • branch
  • 94.71 %
  • toggle
  • 84.65 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 14.000s 79.694us 1 1 100.00
otbn_smoke_vectorized 11.000s 129.216us 1 1 100.00
single_binary 1 1 100.00
otbn_single 8.000s 12.197us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 6.000s 129.187us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 29.198us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 8.000s 324.574us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 24.644us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 38.002us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 29.198us 1 1 100.00
otbn_csr_aliasing 5.000s 24.644us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 76.000s 2989.250us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 20.000s 690.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 43.000s 632.987us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 96.000s 376.365us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 55.000s 536.291us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 287.000s 1651.716us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 13.000s 28.329us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 9.000s 23.994us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 17.000s 360.106us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 6.000s 46.547us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 6.000s 20.265us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 9.000s 1413.511us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 9.000s 1413.511us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 6.000s 129.187us 1 1 100.00
otbn_csr_rw 5.000s 29.198us 1 1 100.00
otbn_csr_aliasing 5.000s 24.644us 1 1 100.00
otbn_same_csr_outstanding 5.000s 186.105us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 6.000s 129.187us 1 1 100.00
otbn_csr_rw 5.000s 29.198us 1 1 100.00
otbn_csr_aliasing 5.000s 24.644us 1 1 100.00
otbn_same_csr_outstanding 5.000s 186.105us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 1 2 50.00
otbn_imem_err 17.000s 103.018us 1 1 100.00
otbn_dmem_err 13.000s 15.442us 0 1 0.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 13.000s 22.775us 1 1 100.00
otbn_controller_ispr_rdata_err 10.000s 912.776us 1 1 100.00
otbn_mac_bignum_acc_err 12.000s 532.585us 1 1 100.00
otbn_urnd_err 10.000s 47.382us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 12.000s 30.289us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 11.000s 27.259us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 9.000s 182.622us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
otbn_tl_intg_err 15.000s 213.308us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 79.000s 252.457us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 14.000s 79.694us 1 1 100.00
sec_cm_data_mem_integrity 0 1 0.00
otbn_dmem_err 13.000s 15.442us 0 1 0.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 17.000s 103.018us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 15.000s 213.308us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 13.000s 28.329us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 17.000s 103.018us 1 1 100.00
otbn_dmem_err 13.000s 15.442us 0 1 0.00
otbn_zero_state_err_urnd 9.000s 23.994us 1 1 100.00
otbn_illegal_mem_acc 12.000s 30.289us 1 1 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 8.000s 12.197us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 17.000s 103.018us 1 1 100.00
otbn_dmem_err 13.000s 15.442us 0 1 0.00
otbn_zero_state_err_urnd 9.000s 23.994us 1 1 100.00
otbn_illegal_mem_acc 12.000s 30.289us 1 1 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 13.000s 28.329us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 17.000s 103.018us 1 1 100.00
otbn_dmem_err 13.000s 15.442us 0 1 0.00
otbn_zero_state_err_urnd 9.000s 23.994us 1 1 100.00
otbn_illegal_mem_acc 12.000s 30.289us 1 1 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 8.000s 12.197us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 11.000s 19.803us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 12.000s 20.093us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 34.000s 273.199us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 34.000s 273.199us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 13.000s 51.264us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 13.000s 56.634us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 50.558us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 50.558us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 7.000s 14.664us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 12.197us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 12.197us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 8.000s 12.197us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 55.000s 536.291us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 8.000s 12.197us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 8.000s 12.197us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 17.000s 45.789us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 8.000s 12.197us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 419.000s 3278.553us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 252.000s 776.005us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_dmem_err 5026420090707885204260542023451901480120080735961855195793517738727903260127 118
UVM_INFO @ 15441713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_urnd_err 77681385749013379295713438148309884370450464532402476552218868043892933795519 113
UVM_ERROR @ 47382485 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 47382485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---