Simulation Results: otp_ctrl

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 80.47 %
  • code
  • 76.70 %
  • assert
  • 94.57 %
  • func
  • 70.14 %
  • line
  • 88.60 %
  • branch
  • 83.13 %
  • cond
  • 89.98 %
  • toggle
  • 78.20 %
  • FSM
  • 43.58 %
Validation stages
V1
88.89%
V2
95.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.470s 53.475us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.110s 244.922us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.690s 93.666us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.230s 47.329us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.130s 105.470us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.200s 59.449us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.370s 993.505us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.230s 47.329us 1 1 100.00
otp_ctrl_csr_aliasing 2.200s 59.449us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.280s 41.925us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.170s 40.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 12.850s 391.313us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.540s 147.319us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 17.360s 1880.212us 1 1 100.00
otp_ctrl_check_fail 3.680s 769.800us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.250s 364.128us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 2.520s 147.549us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 2.120s 181.098us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 9.340s 1819.811us 1 1 100.00
otp_ctrl_parallel_lc_esc 1.940s 102.143us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 14.870s 868.693us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 46.510s 8810.446us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 6.010s 899.171us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 35.910s 2809.041us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.520s 52.700us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.600s 219.050us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.760s 98.455us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.760s 98.455us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.690s 93.666us 1 1 100.00
otp_ctrl_csr_rw 1.230s 47.329us 1 1 100.00
otp_ctrl_csr_aliasing 2.200s 59.449us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.010s 111.359us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.690s 93.666us 1 1 100.00
otp_ctrl_csr_rw 1.230s 47.329us 1 1 100.00
otp_ctrl_csr_aliasing 2.200s 59.449us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.010s 111.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
otp_ctrl_tl_intg_err 8.360s 1293.514us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 8.360s 1293.514us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.110s 244.922us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.110s 244.922us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 1.940s 102.143us 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 1.940s 102.143us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 1.940s 102.143us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 1.940s 102.143us 1 1 100.00
otp_ctrl_macro_errs 46.510s 8810.446us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 1.940s 102.143us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 1.940s 102.143us 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 1.940s 102.143us 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 1.940s 102.143us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 1.940s 102.143us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 1.940s 102.143us 1 1 100.00
otp_ctrl_macro_errs 46.510s 8810.446us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 1.940s 102.143us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 1.940s 102.143us 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.540s 147.319us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 3.680s 769.800us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 2.520s 147.549us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 2.520s 147.549us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 2.520s 147.549us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 2.520s 147.549us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 2.520s 147.549us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.110s 244.922us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 2.520s 147.549us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.110s 244.922us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 142.710s 43087.624us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.250s 364.128us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.110s 244.922us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.110s 244.922us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 46.510s 8810.446us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.560s 7982.943us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 4.080s 171.613us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1306) scoreboard [scoreboard] pwr_otp_idle output is * while expect * within * cycles 2 test runs
otp_ctrl_parallel_key_req 88223360684440374045458944467018406321526435337686322508955382671935099388438 609
UVM_INFO @ 181097571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 108553214375322422125057182548804039243336243644811640368649664159732575785563 2873
UVM_INFO @ 171612873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:764) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 78707663876848207440236708093152208180172957803455251509720605001779768142328 104
UVM_INFO @ 993504567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---