Simulation Results: pwrmgr

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.35 %
  • code
  • 92.79 %
  • assert
  • 97.39 %
  • func
  • 95.88 %
  • line
  • 98.84 %
  • branch
  • 95.62 %
  • cond
  • 93.49 %
  • toggle
  • 90.02 %
  • FSM
  • 86.00 %
Validation stages
V1
66.67%
V2
73.33%
V2S
72.73%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.620s 26.127us 1 1 100.00
csr_hw_reset 0 1 0.00
pwrmgr_csr_hw_reset 3600.029s 0.000us 0 1 0.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.650s 48.976us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.840s 420.690us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.910s 46.803us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
pwrmgr_csr_mem_rw_with_rand_reset 3600.024s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.650s 48.976us 1 1 100.00
pwrmgr_csr_aliasing 0.910s 46.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.820s 108.719us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.820s 108.719us 1 1 100.00
aborted_low_power 1 2 50.00
pwrmgr_aborted_low_power 0.930s 91.156us 1 1 100.00
pwrmgr_lowpower_invalid 0.570s 38.383us 0 1 0.00
reset 1 2 50.00
pwrmgr_reset 2.440s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.910s 151.946us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 2.440s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.930s 117.606us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.650s 68.474us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.600s 24.978us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 10800.036s 0.000us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.640s 20.155us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.330s 77.854us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.330s 77.854us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
pwrmgr_csr_hw_reset 3600.029s 0.000us 0 1 0.00
pwrmgr_csr_rw 0.650s 48.976us 1 1 100.00
pwrmgr_csr_aliasing 0.910s 46.803us 1 1 100.00
pwrmgr_same_csr_outstanding 0.800s 150.937us 1 1 100.00
tl_d_partial_access 3 4 75.00
pwrmgr_csr_hw_reset 3600.029s 0.000us 0 1 0.00
pwrmgr_csr_rw 0.650s 48.976us 1 1 100.00
pwrmgr_csr_aliasing 0.910s 46.803us 1 1 100.00
pwrmgr_same_csr_outstanding 0.800s 150.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 3600.024s 0.000us 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.024s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.540s 972.165us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.930s 117.606us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.730s 1183.075us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.840s 76.382us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.670s 29.860us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.660s 35.209us 1 1 100.00
sec_cm_main_pd_rst_local_esc 0 1 0.00
pwrmgr_glitch 3600.025s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.720s 97.141us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.650s 48.976us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.650s 48.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.880s 188.694us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3600.025s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 7 test runs
pwrmgr_glitch 74915401665072785018578707271555167683543128274640465549654206988237982088188 None
pwrmgr_tl_intg_err 107775775949461602698139334278771650352543137516697360381529611657655678945288 None
pwrmgr_sec_cm 83575765859318357092412288656406309182158618373715361070983256321915444153777 None
pwrmgr_stress_all_with_rand_reset 40134382617615670521254079030055115725350036321295697914217698796086123380235 None
pwrmgr_stress_all 62604054204364679495081540930880069021525991523402988922440322881127864692373 None
pwrmgr_csr_hw_reset 53548148109080680406392452891970148300230124655775173419888052809313332081237 None
pwrmgr_csr_mem_rw_with_rand_reset 92217511659548168637704946049474597574662734435542441590275543552294662535277 None
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 44771650003749847772516835256194478804294853660249857880199617312963897019174 110
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 113639490629785969464865315373989474794841682018539378387434240184253794488068 85
UVM_ERROR @ 188693653 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 188693653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough 1 test run
pwrmgr_lowpower_invalid 37138611032603673036681806686562029620174985035152491197115675370590253084055 82
UVM_INFO @ 38383253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---