Simulation Results: rom_ctrl/192kb

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 94.30 %
  • code
  • 92.46 %
  • assert
  • 97.39 %
  • func
  • 93.05 %
  • line
  • 98.68 %
  • branch
  • 97.83 %
  • cond
  • 97.92 %
  • toggle
  • 94.56 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 17.550s 4181.031us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 28.170s 95.716us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 9.890s 71.422us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 11.810s 343.117us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 10.610s 61.478us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.700s 84.876us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 9.890s 71.422us 1 1 100.00
rom_ctrl_csr_aliasing 10.610s 61.478us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 11.560s 61.244us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 9.780s 64.459us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 10.150s 2.686us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 85.010s 90.240us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 20.990s 59.318us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 10.360s 71.501us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 12.980s 167.828us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 12.980s 167.828us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 28.170s 95.716us 1 1 100.00
rom_ctrl_csr_rw 9.890s 71.422us 1 1 100.00
rom_ctrl_csr_aliasing 10.610s 61.478us 1 1 100.00
rom_ctrl_same_csr_outstanding 10.550s 59.679us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 28.170s 95.716us 1 1 100.00
rom_ctrl_csr_rw 9.890s 71.422us 1 1 100.00
rom_ctrl_csr_aliasing 10.610s 61.478us 1 1 100.00
rom_ctrl_same_csr_outstanding 10.550s 59.679us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 360.590s 16484.603us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 67.050s 4045.656us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 857.890s 419.794us 1 1 100.00
rom_ctrl_tl_intg_err 193.970s 215.447us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 857.890s 419.794us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 857.890s 419.794us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 360.590s 16484.603us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 360.590s 16484.603us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 360.590s 16484.603us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 360.590s 16484.603us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 360.590s 16484.603us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 857.890s 419.794us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 857.890s 419.794us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 17.550s 4181.031us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 17.550s 4181.031us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 17.550s 4181.031us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 193.970s 215.447us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 360.590s 16484.603us 1 1 100.00
rom_ctrl_kmac_err_chk 20.990s 59.318us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 360.590s 16484.603us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 360.590s 16484.603us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 360.590s 16484.603us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 67.050s 4045.656us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 857.890s 419.794us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 60.070s 5801.275us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 50021211035231099547480133934895008331116453183109742613715583722518288347343 85
UVM_INFO @ 2686438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---