Simulation Results: rstmgr

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 97.49 %
  • code
  • 99.28 %
  • assert
  • 98.66 %
  • func
  • 94.53 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.54 %
  • toggle
  • 99.25 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.810s 309.066us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.100s 118.953us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.760s 68.776us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 5.030s 1253.286us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.380s 243.860us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.620s 204.075us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.760s 68.776us 1 1 100.00
rstmgr_csr_aliasing 1.380s 243.860us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.830s 182.491us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.480s 653.361us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.930s 69.368us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.340s 954.532us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.340s 954.532us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.340s 954.532us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.340s 954.532us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 34.190s 10080.079us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.850s 72.701us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.530s 276.661us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.530s 276.661us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.100s 118.953us 1 1 100.00
rstmgr_csr_rw 0.760s 68.776us 1 1 100.00
rstmgr_csr_aliasing 1.380s 243.860us 1 1 100.00
rstmgr_same_csr_outstanding 1.970s 258.819us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.100s 118.953us 1 1 100.00
rstmgr_csr_rw 0.760s 68.776us 1 1 100.00
rstmgr_csr_aliasing 1.380s 243.860us 1 1 100.00
rstmgr_same_csr_outstanding 1.970s 258.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 11.090s 8569.465us 1 1 100.00
rstmgr_tl_intg_err 2.240s 872.199us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.090s 8569.465us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.090s 8569.465us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.240s 872.199us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.920s 117.403us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.340s 1414.206us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.320s 303.068us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.090s 8569.465us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.760s 68.776us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.760s 68.776us 1 1 100.00