Simulation Results: rv_timer

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 94.17 %
  • code
  • 94.66 %
  • assert
  • 98.73 %
  • func
  • 89.12 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.650s 91.660us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.550s 14.037us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.700s 28.936us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.470s 313.750us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.990s 33.897us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.780s 28.048us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.700s 28.936us 1 1 100.00
rv_timer_csr_aliasing 0.990s 33.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.910s 2804.184us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 1.000s 1388.411us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 24.540s 22899.198us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 24.540s 22899.198us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.470s 2460.435us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.860s 44.046us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.600s 16.132us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.390s 785.936us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.390s 785.936us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 14.037us 1 1 100.00
rv_timer_csr_rw 0.700s 28.936us 1 1 100.00
rv_timer_csr_aliasing 0.990s 33.897us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 16.822us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.550s 14.037us 1 1 100.00
rv_timer_csr_rw 0.700s 28.936us 1 1 100.00
rv_timer_csr_aliasing 0.990s 33.897us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 16.822us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.090s 474.561us 1 1 100.00
rv_timer_tl_intg_err 0.890s 167.901us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.890s 167.901us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.600s 34.562us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.650s 89.140us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 9.850s 894.207us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 98921733111586236952774790492176894340606923504930435895833464735519239062548 81
UVM_INFO @ 89140425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---