Simulation Results: spi_device/1r1w

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 81.35 %
  • code
  • 91.26 %
  • assert
  • 95.40 %
  • func
  • 57.39 %
  • line
  • 98.84 %
  • branch
  • 98.09 %
  • cond
  • 95.71 %
  • toggle
  • 74.30 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 33.380s 23877.341us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.190s 47.016us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.940s 575.265us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.000s 1063.223us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.430s 4625.711us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.730s 39.035us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.940s 575.265us 1 1 100.00
spi_device_csr_aliasing 15.430s 4625.711us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.660s 36.054us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.910s 54.921us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.880s 22.794us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.800s 5.286us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.650s 7.264us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.860s 38.062us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.860s 38.062us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 9.040s 4751.051us 1 1 100.00
spi_device_tpm_sts_read 0.970s 146.958us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 6.730s 6689.832us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.850s 1267.707us 1 1 100.00
spi_device_flash_all 0.790s 68.306us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.440s 560.011us 1 1 100.00
spi_device_flash_all 0.790s 68.306us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.440s 560.011us 1 1 100.00
spi_device_flash_all 0.790s 68.306us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 0.790s 68.306us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.470s 1596.074us 1 1 100.00
spi_device_flash_all 0.790s 68.306us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.470s 1596.074us 1 1 100.00
spi_device_flash_all 0.790s 68.306us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.470s 1596.074us 1 1 100.00
spi_device_flash_all 0.790s 68.306us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.470s 1596.074us 1 1 100.00
spi_device_flash_all 0.790s 68.306us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.470s 1596.074us 1 1 100.00
spi_device_flash_all 0.790s 68.306us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.390s 4739.419us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 7.430s 7047.179us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 7.430s 7047.179us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 7.430s 7047.179us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.610s 1003.178us 1 1 100.00
spi_device_read_buffer_direct 2.770s 738.120us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 7.430s 7047.179us 1 1 100.00
spi_device_flash_all 0.790s 68.306us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 0.790s 68.306us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 0.790s 68.306us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 8.220s 4510.673us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 8.220s 4510.673us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 47.530s 32792.846us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 33.380s 23877.341us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 32.330s 3424.432us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 1.360s 66.204us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.940s 17.969us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.670s 42.172us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.420s 54.748us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.420s 54.748us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.190s 47.016us 1 1 100.00
spi_device_csr_rw 1.940s 575.265us 1 1 100.00
spi_device_csr_aliasing 15.430s 4625.711us 1 1 100.00
spi_device_same_csr_outstanding 2.550s 122.493us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.190s 47.016us 1 1 100.00
spi_device_csr_rw 1.940s 575.265us 1 1 100.00
spi_device_csr_aliasing 15.430s 4625.711us 1 1 100.00
spi_device_same_csr_outstanding 2.550s 122.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.220s 66.335us 1 1 100.00
spi_device_tl_intg_err 5.140s 300.187us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.140s 300.187us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 20143068604975207909186305557388123458551209852532671807829979200877421805457 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 4045918 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 4045918 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[999])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 91695274003261666076639146376135074573891752175684367942427921529860388481791 76
UVM_ERROR @ 4656755 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x40 [1000000] vs 0x0 [0])
UVM_ERROR @ 4707755 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2d6 [1011010110] vs 0x0 [0])
UVM_ERROR @ 4761755 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x297 [1010010111] vs 0x0 [0])
UVM_ERROR @ 4767755 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf5 [11110101] vs 0x0 [0])