Simulation Results: spi_host

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.34 %
  • code
  • 91.30 %
  • assert
  • 94.90 %
  • func
  • 87.82 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 2.000s 119.757us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 10.000s 42.839us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 10.000s 119.767us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 12.000s 569.565us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 10.000s 61.430us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 10.000s 46.233us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 10.000s 119.767us 1 1 100.00
spi_host_csr_aliasing 10.000s 61.430us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 10.000s 43.908us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 10.000s 44.725us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 70.370us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 11.000s 73.027us 1 1 100.00
spi_host_error_cmd 10.000s 49.524us 1 1 100.00
spi_host_event 18.000s 5210.681us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 76.240us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 76.240us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 76.240us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 132.000s 3158.771us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 239.053us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 123.342us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 76.240us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 76.240us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 2.000s 119.757us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 2.000s 119.757us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 36.000s 8444.811us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 608.976us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 7.000s 1340.682us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 10.000s 99.955us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 11.000s 73.027us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 10.000s 45.718us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 10.000s 19.023us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 10.000s 344.712us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 10.000s 344.712us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 10.000s 42.839us 1 1 100.00
spi_host_csr_rw 10.000s 119.767us 1 1 100.00
spi_host_csr_aliasing 10.000s 61.430us 1 1 100.00
spi_host_same_csr_outstanding 10.000s 58.662us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 10.000s 42.839us 1 1 100.00
spi_host_csr_rw 10.000s 119.767us 1 1 100.00
spi_host_csr_aliasing 10.000s 61.430us 1 1 100.00
spi_host_same_csr_outstanding 10.000s 58.662us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 10.000s 351.727us 1 1 100.00
spi_host_sec_cm 1.000s 459.274us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 10.000s 351.727us 1 1 100.00