Simulation Results: sram_ctrl/main

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.64 %
  • code
  • 94.83 %
  • assert
  • 98.10 %
  • func
  • 94.00 %
  • block
  • 94.14 %
  • line
  • 95.27 %
  • branch
  • 92.21 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 708.726us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 45.237us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 12.167us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 292.174us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.557us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 709.705us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 12.167us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.557us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 325.000s 22694.450us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 76.000s 1430.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 65.000s 7799.475us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 137.000s 3392.331us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 164.000s 17806.923us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 62.000s 8777.651us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 66.000s 16041.977us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 32.000s 4319.669us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 730.015us 1 1 100.00
sram_ctrl_partial_access_b2b 285.000s 39626.074us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 7.000s 2890.582us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 675.414us 1 1 100.00
sram_ctrl_throughput_w_readback 7.000s 2692.757us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 10.000s 990.291us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 8.000s 354.389us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 285.000s 55224.368us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 23.630us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 6.000s 834.584us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 6.000s 834.584us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 45.237us 1 1 100.00
sram_ctrl_csr_rw 2.000s 12.167us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.557us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 27.527us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 45.237us 1 1 100.00
sram_ctrl_csr_rw 2.000s 12.167us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 15.557us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 27.527us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 34.000s 7167.492us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 308.445us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 566.158us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 308.445us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 566.158us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 990.291us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 990.291us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 12.167us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 32.000s 4319.669us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 32.000s 4319.669us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 32.000s 4319.669us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 66.000s 16041.977us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3602.121s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 34.000s 7167.492us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3602.097s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 708.726us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 708.726us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 32.000s 4319.669us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 308.445us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 66.000s 16041.977us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 308.445us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 308.445us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 708.726us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 308.445us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 23.000s 712.876us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 53466566690658969667326129830264229637256891585305355605091790999755258745186 None
sram_ctrl_mubi_enc_err 102000121097500953152133253644588654567197233872048237803752604209450186605229 None