Simulation Results: sram_ctrl/ret

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.34 %
  • code
  • 81.75 %
  • assert
  • 98.08 %
  • func
  • 94.20 %
  • block
  • 92.19 %
  • line
  • 93.78 %
  • branch
  • 88.23 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 27.816us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 56.900us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 38.568us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 393.468us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 82.513us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 28.420us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 38.568us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 82.513us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 732.318us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 6.000s 789.478us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 12.000s 444.140us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 181.000s 11392.830us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 9.000s 1803.060us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 296.152us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.000s 615.254us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 11.000s 474.199us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 94.756us 1 1 100.00
sram_ctrl_partial_access_b2b 226.000s 13439.089us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 35.529us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 41.485us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 146.989us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1289.158us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 49.035us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 35.000s 11161.166us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 14.088us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 6.000s 126.785us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 6.000s 126.785us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 56.900us 1 1 100.00
sram_ctrl_csr_rw 2.000s 38.568us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 82.513us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 65.873us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 56.900us 1 1 100.00
sram_ctrl_csr_rw 2.000s 38.568us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 82.513us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 65.873us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 1097.989us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 508.598us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 174.068us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 508.598us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 174.068us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1289.158us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1289.158us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 38.568us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 11.000s 474.199us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 474.199us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 474.199us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.000s 615.254us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 1097.989us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 27.816us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 27.816us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 11.000s 474.199us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 508.598us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.000s 615.254us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 508.598us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 508.598us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 27.816us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 508.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 6.000s 751.688us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 59384430046497247398931739770142102069314132386184222624035431570191710199185 None
sram_ctrl_mubi_enc_err 35349733259337765738643855270087741975114258356561894194134087559145039702242 None