Simulation Results: uart

 
25/08/2026 15:30:30 DVSim: v1.52.0 sha: fb9b215 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 83.46 %
  • code
  • 91.51 %
  • assert
  • 97.12 %
  • func
  • 61.76 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 94.75 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 12.510s 5361.664us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.660s 50.778us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.890s 16.340us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.850s 154.226us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.690s 70.205us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.090s 41.480us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.890s 16.340us 1 1 100.00
uart_csr_aliasing 0.690s 70.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 108.730s 202027.252us 1 1 100.00
parity 2 2 100.00
uart_smoke 12.510s 5361.664us 1 1 100.00
uart_tx_rx 108.730s 202027.252us 1 1 100.00
parity_error 2 2 100.00
uart_intr 18.610s 31845.315us 1 1 100.00
uart_rx_parity_err 5.320s 7914.101us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 108.730s 202027.252us 1 1 100.00
uart_intr 18.610s 31845.315us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 86.410s 168636.703us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 200.820s 217661.076us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 41.190s 178974.403us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 18.610s 31845.315us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 18.610s 31845.315us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 18.610s 31845.315us 1 1 100.00
perf 1 1 100.00
uart_perf 325.020s 13816.915us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.310s 3332.325us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.310s 3332.325us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 6.450s 13184.603us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 15.190s 45828.199us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.510s 390.234us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.670s 2916.604us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 311.340s 113196.151us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 157.970s 190381.599us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.710s 42.980us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.580s 59.974us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.120s 45.820us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.120s 45.820us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.660s 50.778us 1 1 100.00
uart_csr_rw 0.890s 16.340us 1 1 100.00
uart_csr_aliasing 0.690s 70.205us 1 1 100.00
uart_same_csr_outstanding 1.030s 17.013us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.660s 50.778us 1 1 100.00
uart_csr_rw 0.890s 16.340us 1 1 100.00
uart_csr_aliasing 0.690s 70.205us 1 1 100.00
uart_same_csr_outstanding 1.030s 17.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.040s 130.133us 1 1 100.00
uart_tl_intg_err 1.360s 97.659us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.360s 97.659us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 3.250s 721.210us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 67077264597405261258950223428441762792315493569978489636894640200227340385746 83
UVM_ERROR @ 8419459339 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 8419681561 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 8836644107 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 8836644107 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0