Simulation Results: adc_ctrl

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 70.80 %
  • code
  • 97.36 %
  • assert
  • 96.43 %
  • func
  • 18.61 %
  • line
  • 99.05 %
  • branch
  • 98.45 %
  • cond
  • 94.71 %
  • toggle
  • 100.00 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 11.010s 5906.574us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.340s 758.036us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.570s 469.704us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 63.490s 52579.068us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.250s 579.803us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.720s 377.487us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.570s 469.704us 1 1 100.00
adc_ctrl_csr_aliasing 1.250s 579.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 56.810s 53828.756us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 28.110s 57968.822us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 33.480s 19662.838us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 17.990s 34629.132us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 20.870s 21968.793us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 102.100s 47065.040us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 24.160s 25029.934us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 12.930s 58755.582us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 3.140s 5210.285us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 33.170s 37250.400us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 121.080s 104973.396us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 38.030s 30100.936us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.220s 385.895us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.400s 389.731us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 3.060s 676.440us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 3.060s 676.440us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.340s 758.036us 1 1 100.00
adc_ctrl_csr_rw 1.570s 469.704us 1 1 100.00
adc_ctrl_csr_aliasing 1.250s 579.803us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.660s 4300.193us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.340s 758.036us 1 1 100.00
adc_ctrl_csr_rw 1.570s 469.704us 1 1 100.00
adc_ctrl_csr_aliasing 1.250s 579.803us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.660s 4300.193us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.860s 8590.351us 1 1 100.00
adc_ctrl_tl_intg_err 4.780s 5106.470us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 4.780s 5106.470us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 9.450s 27133.103us 1 1 100.00