Simulation Results: aes/unmasked

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.09 %
  • code
  • 89.54 %
  • assert
  • 97.73 %
  • func
  • 74.00 %
  • block
  • 89.26 %
  • line
  • 91.64 %
  • branch
  • 79.65 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 73.529us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 69.783us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 60.567us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 52.428us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 934.027us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 108.458us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 96.986us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 52.428us 1 1 100.00
aes_csr_aliasing 2.000s 108.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 69.783us 1 1 100.00
aes_config_error 3.000s 94.008us 1 1 100.00
aes_stress 3.000s 58.841us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 69.783us 1 1 100.00
aes_config_error 3.000s 94.008us 1 1 100.00
aes_stress 3.000s 58.841us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 58.841us 1 1 100.00
aes_b2b 3.000s 212.020us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 58.841us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 69.783us 1 1 100.00
aes_config_error 3.000s 94.008us 1 1 100.00
aes_stress 3.000s 58.841us 1 1 100.00
aes_alert_reset 2.000s 73.180us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 61.363us 1 1 100.00
aes_config_error 3.000s 94.008us 1 1 100.00
aes_alert_reset 2.000s 73.180us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 79.375us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 356.856us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 73.180us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 58.841us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 58.841us 1 1 100.00
aes_sideload 2.000s 132.763us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 125.995us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 4.000s 217.936us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 96.084us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 967.864us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 967.864us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 60.567us 1 1 100.00
aes_csr_rw 2.000s 52.428us 1 1 100.00
aes_csr_aliasing 2.000s 108.458us 1 1 100.00
aes_same_csr_outstanding 2.000s 130.637us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 60.567us 1 1 100.00
aes_csr_rw 2.000s 52.428us 1 1 100.00
aes_csr_aliasing 2.000s 108.458us 1 1 100.00
aes_same_csr_outstanding 2.000s 130.637us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 267.856us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 4.000s 109.145us 0 1 0.00
aes_control_fi 2.000s 56.256us 1 1 100.00
aes_cipher_fi 8.000s 10039.998us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 295.694us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 295.694us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 295.694us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 295.694us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 96.121us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 731.157us 1 1 100.00
aes_tl_intg_err 4.000s 231.908us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 4.000s 231.908us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 73.180us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 295.694us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 295.694us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 69.783us 1 1 100.00
aes_stress 3.000s 58.841us 1 1 100.00
aes_alert_reset 2.000s 73.180us 1 1 100.00
aes_core_fi 3.000s 66.187us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 94.008us 1 1 100.00
aes_stress 3.000s 58.841us 1 1 100.00
aes_core_fi 3.000s 66.187us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 295.694us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 90.404us 1 1 100.00
aes_stress 3.000s 58.841us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 58.841us 1 1 100.00
aes_sideload 2.000s 132.763us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 90.404us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 90.404us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 90.404us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 90.404us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 90.404us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 58.841us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 58.841us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 109.145us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 4.000s 109.145us 0 1 0.00
aes_control_fi 2.000s 56.256us 1 1 100.00
aes_cipher_fi 8.000s 10039.998us 0 1 0.00
aes_ctr_fi 2.000s 53.049us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 109.145us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 4.000s 109.145us 0 1 0.00
aes_control_fi 2.000s 56.256us 1 1 100.00
aes_cipher_fi 8.000s 10039.998us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 8.000s 10039.998us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 109.145us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 109.145us 0 1 0.00
aes_control_fi 2.000s 56.256us 1 1 100.00
aes_ctr_fi 2.000s 53.049us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 109.145us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 4.000s 109.145us 0 1 0.00
aes_control_fi 2.000s 56.256us 1 1 100.00
aes_cipher_fi 8.000s 10039.998us 0 1 0.00
aes_ctr_fi 2.000s 53.049us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 73.180us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 4.000s 109.145us 0 1 0.00
aes_control_fi 2.000s 56.256us 1 1 100.00
aes_cipher_fi 8.000s 10039.998us 0 1 0.00
aes_ctr_fi 2.000s 53.049us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 4.000s 109.145us 0 1 0.00
aes_control_fi 2.000s 56.256us 1 1 100.00
aes_cipher_fi 8.000s 10039.998us 0 1 0.00
aes_ctr_fi 2.000s 53.049us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 109.145us 0 1 0.00
aes_control_fi 2.000s 56.256us 1 1 100.00
aes_ctr_fi 2.000s 53.049us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 109.145us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 4.000s 109.145us 0 1 0.00
aes_control_fi 2.000s 56.256us 1 1 100.00
aes_cipher_fi 8.000s 10039.998us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 5.000s 342.110us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 68115444326369693287045472284430794527733660123467166606399448829215576236722 2463
UVM_INFO @ 267855647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 66692190269932601312687073141618748023375668290823768715711412515313270112154 11400
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 32691295204287132136650224597552091113440856146682569335448613434723098501402 147
UVM_INFO @ 10039998148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 115692613715201841156809934755226779759282410380698640064189376192155590635049 357
UVM_INFO @ 342109901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---