Simulation Results

Simulation Results: chip

26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
71.37 %

code
75.69 %

assert
96.61 %

func
41.82 %

line
93.73 %

branch
93.15 %

cond
88.07 %

toggle
70.19 %

FSM
33.33 %

Validation stages

V1		100.00%
V2		84.79%
V2S		100.00%
V3		56.00%
unmapped		12.50%

17/17 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				3	3	100.00
	chip_sw_example_rom	95.760s	1935.139us	1	1	100.00
	chip_sw_example_manufacturer	229.380s	2604.830us	1	1	100.00
	chip_sw_example_concurrency	247.240s	2809.371us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	600.200s	14129.856us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	610.680s	11868.094us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	2823.560s	37661.914us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	9413.930s	71688.932us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	1047.390s	14573.076us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	9413.930s	71688.932us	1	1	100.00
	chip_csr_rw	610.680s	11868.094us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	4.900s	36.807us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	380.040s	3735.844us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	380.040s	3735.844us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	380.040s	3735.844us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	450.920s	4780.689us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	450.920s	4780.689us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	484.700s	4350.026us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	428.470s	4445.333us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	398.920s	3612.920us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	552.340s	4460.430us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1224.400s	8209.860us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	366.620s	4610.764us	1	1	100.00

223/263 passed

84.79 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	521.740s	12151.747us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	521.740s	12151.747us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	247.560s	3292.109us	1	1	100.00
chip_sw_sleep_pin_wake				0	1	0.00
	chip_sw_sleep_pin_wake	222.070s	3111.989us	0	1	0.00
chip_sw_sleep_pin_retention				0	1	0.00
	chip_sw_sleep_pin_retention	234.480s	3251.359us	0	1	0.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	526.390s	8394.400us	1	1	100.00
	chip_tap_straps_testunlock0	220.940s	3954.231us	1	1	100.00
	chip_tap_straps_rma	155.850s	2941.527us	1	1	100.00
	chip_tap_straps_prod	133.020s	2789.689us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	521.510s	4598.409us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	521.510s	4598.409us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	752.200s	7714.296us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	2248.500s	14637.128us	0	1	0.00
chip_sw_ast_sys_clk_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4225.790s	18709.882us	1	1	100.00
	chip_sw_aes_enc_jitter_en	250.440s	3008.496us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	979.760s	7341.661us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	188.860s	2819.306us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	2144.050s	12497.355us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	243.070s	3130.413us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	490.690s	4583.554us	1	1	100.00
	chip_sw_clkmgr_jitter	205.190s	2572.214us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	296.930s	2788.928us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				1	2	50.00
	chip_sw_sensor_ctrl_alert	806.210s	7652.823us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	145.170s	2191.627us	0	1	0.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	227.220s	2998.956us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				0	1	0.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	145.170s	2191.627us	0	1	0.00
chip_sw_smoketest				16	16	100.00
	chip_sw_aes_smoketest	240.660s	3174.099us	1	1	100.00
	chip_sw_aon_timer_smoketest	274.330s	2626.729us	1	1	100.00
	chip_sw_clkmgr_smoketest	214.030s	2579.930us	1	1	100.00
	chip_sw_csrng_smoketest	174.000s	2362.774us	1	1	100.00
	chip_sw_entropy_src_smoketest	972.490s	5886.840us	1	1	100.00
	chip_sw_gpio_smoketest	262.710s	2996.984us	1	1	100.00
	chip_sw_hmac_smoketest	313.110s	2931.504us	1	1	100.00
	chip_sw_kmac_smoketest	233.050s	3034.515us	1	1	100.00
	chip_sw_otbn_smoketest	1275.960s	7364.403us	1	1	100.00
	chip_sw_pwrmgr_smoketest	444.050s	5704.922us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	417.940s	5049.764us	1	1	100.00
	chip_sw_rv_plic_smoketest	226.000s	2925.733us	1	1	100.00
	chip_sw_rv_timer_smoketest	275.990s	3153.412us	1	1	100.00
	chip_sw_rstmgr_smoketest	215.560s	2748.945us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	236.170s	2973.216us	1	1	100.00
	chip_sw_uart_smoketest	263.810s	2588.746us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	256.600s	3161.751us	1	1	100.00
chip_sw_rom_functests				1	1	100.00
	rom_keymgr_dpe_functest	365.490s	3579.969us	1	1	100.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	20374.760s	127871.988us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3608.330s	15887.613us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	1487.940s	18001.093us	0	1	0.00
chip_sw_power_idle_load				1	1	100.00
	chip_sw_power_idle_load	490.360s	4260.318us	1	1	100.00
chip_sw_power_sleep_load				1	1	100.00
	chip_sw_power_sleep_load	444.610s	9442.462us	1	1	100.00
chip_sw_exit_test_unlocked_bootstrap				0	1	0.00
	chip_sw_exit_test_unlocked_bootstrap	13200.141s	0.000us	0	1	0.00
tl_d_oob_addr_access				1	1	100.00
	chip_tl_errors	239.230s	8214.446us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	chip_tl_errors	239.230s	8214.446us	1	1	100.00
tl_d_outstanding_access				3	4	75.00
	chip_csr_aliasing	9413.930s	71688.932us	1	1	100.00
	chip_same_csr_outstanding	174.120s	3134.838us	0	1	0.00
	chip_csr_hw_reset	600.200s	14129.856us	1	1	100.00
	chip_csr_rw	610.680s	11868.094us	1	1	100.00
tl_d_partial_access				3	4	75.00
	chip_csr_aliasing	9413.930s	71688.932us	1	1	100.00
	chip_same_csr_outstanding	174.120s	3134.838us	0	1	0.00
	chip_csr_hw_reset	600.200s	14129.856us	1	1	100.00
	chip_csr_rw	610.680s	11868.094us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	51.190s	1776.468us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.830s	36.689us	1	1	100.00
	xbar_smoke_large_delays	36.270s	5573.868us	1	1	100.00
	xbar_smoke_slow_rsp	54.120s	4531.577us	1	1	100.00
	xbar_random_zero_delays	12.850s	122.449us	1	1	100.00
	xbar_random_large_delays	130.280s	18036.640us	1	1	100.00
	xbar_random_slow_rsp	31.880s	2300.839us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	9.400s	93.150us	1	1	100.00
	xbar_error_and_unmapped_addr	22.890s	259.977us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	8.750s	83.486us	1	1	100.00
	xbar_error_and_unmapped_addr	22.890s	259.977us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	54.330s	1067.311us	1	1	100.00
	xbar_access_same_device_slow_rsp	464.420s	45350.582us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	11.620s	427.427us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	177.840s	2942.647us	1	1	100.00
	xbar_stress_all_with_error	171.290s	2972.447us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	47.330s	86.211us	1	1	100.00
	xbar_stress_all_with_reset_error	17.340s	77.484us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3608.330s	15887.613us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	3389.980s	34610.879us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3580.290s	20695.994us	1	1	100.00
rom_e2e_boot_policy_valid				14	15	93.33
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2911.180s	10572.235us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	3994.090s	15341.795us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	4113.590s	15899.603us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	3726.070s	16461.855us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	3830.600s	15998.339us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	2953.570s	11907.111us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	3905.920s	17390.860us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	3854.830s	15389.970us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	3927.520s	15727.694us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	176.400s	3399.540us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	5338.680s	19165.834us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	6928.480s	24664.950us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	6687.230s	25418.812us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	6692.260s	25551.453us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	6849.970s	24096.841us	1	1	100.00
rom_e2e_sigverify_always				14	15	93.33
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	5270.650s	23344.951us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	7287.570s	46211.163us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	6758.340s	28845.657us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	6594.820s	32893.349us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	7014.160s	32716.391us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	3681.550s	29456.160us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	3961.700s	28967.428us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	3812.800s	19886.227us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	3891.560s	20061.461us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	3749.290s	18779.453us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	2701.150s	10403.008us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	3585.090s	14175.342us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	101.060s	2348.540us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	3844.370s	25151.146us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	3712.170s	19885.488us	1	1	100.00
rom_e2e_asm_init				5	5	100.00
	rom_e2e_asm_init_test_unlocked0	2923.200s	11064.463us	1	1	100.00
	rom_e2e_asm_init_dev	3717.240s	15715.382us	1	1	100.00
	rom_e2e_asm_init_prod	4034.340s	17179.945us	1	1	100.00
	rom_e2e_asm_init_prod_end	4066.320s	15798.005us	1	1	100.00
	rom_e2e_asm_init_rma	3744.950s	15959.473us	1	1	100.00
rom_e2e_keymgr_dpe_init				3	3	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_meas	7500.160s	31583.264us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_no_meas	7080.870s	29829.753us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas	7759.300s	29068.962us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	4101.680s	18604.936us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.159s	0.000us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.159s	0.000us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	274.860s	3338.928us	1	1	100.00
	chip_sw_aes_enc_jitter_en	250.440s	3008.496us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	200.310s	2878.966us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	229.640s	3169.191us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	927.540s	5832.494us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	265.260s	3026.848us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	501.540s	5114.781us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	434.900s	4980.136us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	558.030s	5036.848us	1	1	100.00
	chip_plic_all_irqs_10	273.830s	3417.128us	1	1	100.00
	chip_plic_all_irqs_20	460.350s	3706.900us	1	1	100.00
chip_sw_alert_handler_entropy				0	1	0.00
	chip_sw_alert_handler_entropy	264.860s	2946.316us	0	1	0.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1187.900s	11461.074us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	307.410s	3911.618us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	218.440s	2866.058us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	326.220s	3286.447us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1513.270s	9063.918us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1191.530s	7479.416us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	967.180s	7693.405us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11737.460s	254687.882us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	264.990s	3545.991us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	444.050s	5704.922us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	264.990s	3545.991us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	581.920s	8845.765us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	581.920s	8845.765us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	390.230s	6680.934us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	503.890s	5424.234us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	814.280s	5644.552us	1	1	100.00
	chip_sw_aes_idle	229.640s	3169.191us	1	1	100.00
	chip_sw_hmac_enc_idle	283.390s	3098.380us	1	1	100.00
	chip_sw_kmac_idle	215.460s	3205.687us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	293.960s	3607.644us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	462.790s	4565.689us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	351.450s	4137.820us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	338.920s	3340.278us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	1161.760s	10492.013us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	506.840s	3593.908us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	449.490s	4521.182us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	500.150s	4293.622us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	512.460s	4566.837us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	446.660s	4230.513us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	529.500s	4656.303us	1	1	100.00
	chip_sw_ast_clk_outputs	752.200s	7714.296us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	1014.670s	15328.469us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	500.150s	4293.622us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	512.460s	4566.837us	1	1	100.00
chip_sw_clkmgr_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4225.790s	18709.882us	1	1	100.00
	chip_sw_aes_enc_jitter_en	250.440s	3008.496us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	979.760s	7341.661us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	188.860s	2819.306us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	2144.050s	12497.355us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	243.070s	3130.413us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	490.690s	4583.554us	1	1	100.00
	chip_sw_clkmgr_jitter	205.190s	2572.214us	1	1	100.00
chip_sw_clkmgr_extended_range				8	8	100.00
	chip_sw_clkmgr_jitter_reduced_freq	214.880s	2923.713us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4547.750s	25224.915us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	198.260s	2817.992us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	213.960s	2267.735us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1080.280s	8897.695us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	252.630s	3324.730us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	419.490s	3911.713us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	5842.740s	34596.502us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	752.200s	7714.296us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				0	1	0.00
	chip_sw_clkmgr_sleep_frequency	454.100s	4383.360us	0	1	0.00
chip_sw_clkmgr_reset_frequency				0	1	0.00
	chip_sw_clkmgr_reset_frequency	693.440s	10887.027us	0	1	0.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	434.900s	4980.136us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1513.270s	9063.918us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1226.040s	6787.361us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	358.780s	4025.940us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	865.040s	9395.496us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	227.560s	3125.889us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	6801.530s	32363.527us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	181.970s	2756.796us	1	1	100.00
	chip_sw_edn_entropy_reqs	702.240s	6204.675us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	181.970s	2756.796us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1226.040s	6787.361us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	252.220s	2358.640us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	243.410s	2840.307us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	188.860s	2819.306us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	283.390s	3098.380us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1942.510s	11442.543us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	2182.160s	12010.400us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	490.180s	4463.965us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	512.610s	5315.790us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	538.840s	4685.717us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	377.770s	4094.635us	1	1	100.00
chip_sw_keymgr_dpe_key_derivation				2	2	100.00
	chip_sw_keymgr_dpe_key_derivation	1972.010s	11093.934us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	2144.050s	12497.355us	1	1	100.00
chip_sw_keymgr_dpe_sideload_kmac				1	1	100.00
	chip_sw_keymgr_dpe_sideload_kmac	1182.610s	8252.996us	1	1	100.00
chip_sw_keymgr_dpe_sideload_aes				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	927.540s	5832.494us	1	1	100.00
chip_sw_keymgr_dpe_sideload_otbn				0	1	0.00
	chip_sw_keymgr_dpe_sideload_otbn	3600.148s	0.000us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	230.710s	2795.125us	1	1	100.00
	chip_sw_kmac_mode_kmac	290.660s	3445.747us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	243.070s	3130.413us	1	1	100.00
chip_sw_kmac_app_keymgr_dpe				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1972.010s	11093.934us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	1131.160s	15138.247us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	433.010s	6151.854us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1675.620s	8811.374us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	215.460s	3205.687us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	501.540s	5114.781us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	526.390s	8394.400us	1	1	100.00
	chip_tap_straps_rma	155.850s	2941.527us	1	1	100.00
	chip_tap_straps_prod	133.020s	2789.689us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	244.080s	2527.498us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	1131.160s	15138.247us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	1131.160s	15138.247us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	1131.160s	15138.247us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_prod	1949.250s	11538.923us	1	1	100.00
chip_sw_lc_ctrl_broadcast				18	21	85.71
	chip_sw_rram_rma_unlocked	316.100s	10010.240us	0	1	0.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	310.650s	3847.202us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	744.640s	5965.546us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	773.980s	6408.477us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	738.650s	6421.639us	0	1	0.00
	chip_sw_lc_ctrl_transition	1131.160s	15138.247us	1	1	100.00
	chip_sw_rram_ctrl_lc_rw_en	426.990s	5299.627us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1972.010s	11093.934us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	884.390s	15286.020us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	601.540s	7436.997us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	1014.670s	15328.469us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	506.840s	3593.908us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	449.490s	4521.182us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	500.150s	4293.622us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	512.460s	4566.837us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	446.660s	4230.513us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	529.500s	4656.303us	1	1	100.00
	chip_tap_straps_dev	526.390s	8394.400us	1	1	100.00
	chip_tap_straps_rma	155.850s	2941.527us	1	1	100.00
	chip_tap_straps_prod	133.020s	2789.689us	1	1	100.00
	chip_rv_dm_lc_disabled	176.860s	8037.236us	0	1	0.00
chip_lc_scrap				3	4	75.00
	chip_sw_lc_ctrl_rma_to_scrap	412.580s	5518.787us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	569.830s	12199.941us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	456.670s	10398.084us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	574.500s	10702.816us	0	1	0.00
chip_lc_test_locked				0	2	0.00
	chip_sw_lc_walkthrough_testunlocks	3307.130s	60000.000us	0	1	0.00
	chip_rv_dm_lc_disabled	176.860s	8037.236us	0	1	0.00
chip_sw_lc_walkthrough				1	5	20.00
	chip_sw_lc_walkthrough_dev	1488.520s	15377.874us	0	1	0.00
	chip_sw_lc_walkthrough_prod	1751.130s	20989.381us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	1318.670s	18910.531us	1	1	100.00
	chip_sw_lc_walkthrough_rma	1000.530s	12405.035us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	3307.130s	60000.000us	0	1	0.00
chip_sw_lc_ctrl_volatile_raw_unlock				3	3	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock	265.170s	6266.668us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	301.230s	6734.545us	1	1	100.00
	rom_volatile_raw_unlock	250.510s	5440.681us	1	1	100.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	4128.450s	17963.118us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4225.790s	18709.882us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	814.280s	5644.552us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	814.280s	5644.552us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	814.280s	5644.552us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	357.770s	3358.161us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	1131.160s	15138.247us	1	1	100.00
chip_sw_otp_ctrl_keys				3	4	75.00
	chip_sw_otbn_mem_scramble	357.770s	3358.161us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1972.010s	11093.934us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	504.040s	4131.857us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3410.890s	60000.000us	0	1	0.00
chip_sw_otp_ctrl_entropy				3	4	75.00
	chip_sw_otbn_mem_scramble	357.770s	3358.161us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1972.010s	11093.934us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	504.040s	4131.857us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3410.890s	60000.000us	0	1	0.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	1131.160s	15138.247us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	535.980s	5602.740us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	244.080s	2527.498us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				4	5	80.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	310.650s	3847.202us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	744.640s	5965.546us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	773.980s	6408.477us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	738.650s	6421.639us	0	1	0.00
	chip_sw_lc_ctrl_transition	1131.160s	15138.247us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	994.430s	6901.272us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	416.930s	6415.070us	1	1	100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	182.250s	2457.290us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	159.480s	2181.385us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	622.970s	8056.522us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_por_reset	302.190s	4204.661us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1182.910s	19411.019us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				2	2	100.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	1102.590s	13507.718us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	581.920s	8845.765us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	312.160s	3711.902us	0	1	0.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	516.120s	4719.460us	1	1	100.00
chip_sw_pwrmgr_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	416.930s	6415.070us	1	1	100.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	364.380s	4155.957us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1998.170s	27568.760us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	440.590s	6281.973us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	247.320s	2943.944us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	524.960s	7156.360us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	725.270s	6631.752us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	978.860s	9605.887us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	2171.460s	25642.139us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	214.180s	2810.885us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	434.900s	4980.136us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	884.390s	15286.020us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	884.390s	15286.020us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	978.860s	9605.887us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	524.960s	7156.360us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	516.120s	4719.460us	1	1	100.00
	chip_sw_pwrmgr_smoketest	444.050s	5704.922us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	380.020s	5148.367us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	396.940s	4293.508us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	394.810s	3676.416us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1187.900s	11461.074us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	244.080s	2698.224us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	434.900s	4980.136us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1191.530s	7479.416us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	581.470s	4665.097us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	626.200s	4521.943us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	243.230s	3131.751us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				0	1	0.00
	chip_sw_rv_core_ibex_icache_invalidate	3410.890s	60000.000us	0	1	0.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	396.940s	4293.508us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	396.940s	4293.508us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	190.510s	2610.943us	1	1	100.00
chip_jtag_csr_rw				0	1	0.00
	chip_jtag_csr_rw	105.760s	2403.949us	0	1	0.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	1547.990s	19282.232us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	380.020s	5148.367us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	234.850s	2920.491us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	243.150s	2749.678us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	155.850s	2941.527us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	176.860s	8037.236us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	558.030s	5036.848us	1	1	100.00
	chip_plic_all_irqs_10	273.830s	3417.128us	1	1	100.00
	chip_plic_all_irqs_20	460.350s	3706.900us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	182.750s	2960.236us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	217.210s	3042.669us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3608.330s	15887.613us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	364.260s	5142.118us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	267.250s	2557.530us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	259.600s	3056.188us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	199.610s	2332.748us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	504.040s	4131.857us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	490.690s	4583.554us	1	1	100.00
chip_sw_sleep_sram_ret_contents				0	2	0.00
	chip_sw_sleep_sram_ret_contents_no_scramble	188.980s	2467.009us	0	1	0.00
	chip_sw_sleep_sram_ret_contents_scramble	268.950s	3350.064us	0	1	0.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	601.540s	7436.997us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	434.900s	4980.136us	1	1	100.00
	chip_sw_data_integrity_escalation	521.510s	4598.409us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	725.270s	6631.752us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1058.660s	22426.274us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	267.770s	3612.220us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	340.680s	3171.718us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	428.040s	4421.415us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1058.660s	22426.274us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1058.660s	22426.274us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2864.620s	20610.813us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2864.620s	20610.813us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	341.870s	4998.066us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.159s	0.000us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	193.020s	2932.550us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	205.540s	2311.675us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	363.550s	3937.305us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	365.710s	3878.914us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	954.810s	8208.707us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	6310.350s	31550.145us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	2305.260s	11919.944us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	206.950s	2746.316us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	262.800s	2940.029us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	123.960s	2088.372us	1	1	100.00

14/25 passed

56.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	12802.970s	72317.300us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1371.210s	6457.942us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	119.270s	2205.193us	0	1	0.00
	rom_e2e_jtag_debug_dev	80.410s	1834.179us	0	1	0.00
	rom_e2e_jtag_debug_rma	94.090s	2130.039us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	110.050s	2057.916us	0	1	0.00
	rom_e2e_jtag_inject_dev	114.490s	1933.131us	0	1	0.00
	rom_e2e_jtag_inject_rma	95.060s	1761.866us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	44.708s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	402.220s	3784.664us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	387.010s	2772.780us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	889.890s	4627.743us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	981.030s	6481.299us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	287.430s	2534.842us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	237.590s	2992.254us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	398.250s	5897.525us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	416.730s	4104.541us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	978.860s	9605.887us	1	1	100.00
chip_sw_rom_ctrl_digests				1	1	100.00
	chip_sw_kmac_app_rom	433.010s	6151.854us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	119.270s	2205.193us	0	1	0.00
	rom_e2e_jtag_debug_dev	80.410s	1834.179us	0	1	0.00
	rom_e2e_jtag_debug_rma	94.090s	2130.039us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				0	1	0.00
	chip_sw_rv_dm_access_after_escalation_reset	250.270s	3058.037us	0	1	0.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	434.900s	4980.136us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	6367.860s	38243.603us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	6367.860s	38243.603us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				0	1	0.00
	chip_sw_spi_device_pinmux_sleep_retention	200.110s	2265.407us	0	1	0.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	450.920s	4780.689us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3810.690s	18476.305us	1	1	100.00

unmapped

1/8 passed

12.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	8	12.50
	chip_sw_rstmgr_rst_cnsty_escalation	50.660s	10.340us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	1431.740s	17984.364us	0	1	0.00
	chip_sw_otp_ctrl_descrambling	218.980s	2566.507us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	179.610s	2387.900us	0	1	0.00
	chip_sw_pwrmgr_sleep_wake_5_bug	11.360s	0.000us	0	1	0.00
	ate_bootstrap_flash_erase	695.390s	10010.100us	0	1	0.00
	ate_bootstrap_one_frame	10800.154s	0.000us	0	1	0.00
	ate_bootstrap_disjoint	10800.147s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error				14 test runs
	chip_sw_sleep_pin_wake	32951407061787552931191929914216054721790199916566048500278597507115795887973	382	UVM_INFO @ 3111.989328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_pin_retention	68997974491931311271129280969915108417305888819110688327458892153747707749404	379	UVM_INFO @ 3251.358920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_spi_device_pinmux_sleep_retention	100736109065551484241719532056200923679781982756878874864163573339826255311158	374	UVM_INFO @ 2265.407220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	65768841463616676236396620051194256419971063730022045178087093758505698045518	392	UVM_INFO @ 7156.359672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	114743647319604627879309552329339515321398912186866536526295198441276224308913	377	UVM_INFO @ 3711.902152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_por_reset	99563991955401813761351037707332808555521282370749683264028490981649169288284	388	UVM_INFO @ 4204.660674 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_no_scramble	76515820652209291387720865462353850371733565651385685295600155523071429507611	377	UVM_INFO @ 2467.008600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_scramble	22817436700639963819021633575398309732039533099726228821305030865070094504701	381	UVM_INFO @ 3350.063982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	13894555379243770471081366273959492197541588293664203141996522228633455917862	372	UVM_INFO @ 2191.627164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_clkmgr_sleep_frequency	93504845201670749494959722552663749337539491788290201308731139995333694772514	407	UVM_INFO @ 4383.359848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	16207071136340093662097681579170422640193398178793593613839800635672866251724	374	UVM_INFO @ 2181.384972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_lowpower_cancel	19842703412444480793150768176104371024020935015418408278087560829003439412363	372	UVM_INFO @ 2387.899848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_wake_ups	2418222960127183589751008546628137304698375641079869628497480874046589973321	373	UVM_INFO @ 2457.289902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_dm_access_after_wakeup	15746832067413410286469804493703313590756008031351647414753518879767246566720	390	UVM_INFO @ 2749.677662 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				5 test runs
	chip_sw_exit_test_unlocked_bootstrap	90482213535496365667427101227806661982927537915329182239158697999793876830347	None
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53989633977953592765246393538357653897896480846162826982037584498744568512654	None
	chip_sw_keymgr_dpe_sideload_otbn	74955108822078315119631761684439497179582847108995038153058017628044364225159	None
	ate_bootstrap_one_frame	19173436683397597103538541497189359047971640958425845449063221136962742432828	None
	ate_bootstrap_disjoint	62953475096117854787700536535115892765045822933297855779384935136026405309084	None
Error-[NOA] Null object access				5 test runs
	chip_sw_otp_ctrl_rot_auth_config	15816846963701683360081048492958065339091575034025283305924028138511997035919	386	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	84304988715220438963062848362778083827210670623991177722555530724314951654954	403	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	3494166740197346162103759116270783276954278609155810051252698820599535485635	381	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	102012719385160326442733387383102164690471834035733583927551269892452940868317	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	80203797666860618457794603635827635333146363655785273607662427881858833926738	381	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	17336804685277597391381329077819581612082409415574940046333429864431601275785	433	UVM_INFO @ 15377.874360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	84623270840007435113664049404500240475560020652909154904279198727615905292267	433	UVM_INFO @ 20989.381025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	27617395180977305027415117522263633563465685235546192759228328880789707622574	405	UVM_INFO @ 12405.034920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [] vs [*])				3 test runs
	rom_e2e_jtag_debug_test_unlocked0	11324117826758469380541992908030075061358647580799690535657820703984704262423	359	UVM_INFO @ 2205.192500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_dev	74947959236699941184341713195266907821213978336319932383584980735695993135872	359	UVM_INFO @ 1834.179500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_rma	5841573847785614398615513817705184026795672931348439859944612262326193865451	359	UVM_INFO @ 2130.039000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue				2 test runs
	chip_sw_lc_walkthrough_testunlocks	40547864950700682827944050280286363299126274207985449847757086341324903577703	513	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_core_ibex_icache_invalidate	107220845948070183496108814882150271513035146199221588123718599671978061843555	377	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	88867694910962523716349028050576997093386416399922625656898995472597473027696	377	UVM_ERROR @ 2943.943656 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 2943.943656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	75015811730766181307872966488864421239080141164222103809014714509481800242227	471	UVM_ERROR @ 27568.760360 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 27568.760360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error				2 test runs
	chip_sw_alert_handler_lpg_sleep_mode_pings	55812676331097373131560615383192118203077902565245405117583786202972718554479	373	UVM_INFO @ 3286.446504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_alert_handler_entropy	83449665289999305635649563914258414299933262573477861846731875115281506140402	453	UVM_INFO @ 2946.316360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	87540454488127175789690911431587965163315372426362807562770230398973311192004	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	56212225541377463423043701129734206403862090529283113772040659896251982065274	None	---- STDERR ---- Another command (pid=395613) is running. Waiting for it to complete on the server (server_pid=208610)... Another command (pid=413134) is running. Waiting for it to complete on the server (server_pid=208610)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert fatal triggered unexpectedly				1 test run
	chip_same_csr_outstanding	90683673748203635874244888402348817746786593211804552189779665524386588184396	282	UVM_INFO @ 3134.838252 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	16870723707050985593129254970091877975738361293607749484297082155172561409640	365	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	52244942828949892247636833187829867581458186921608674281961763293381714989740	391	UVM_INFO @ 2557.529555 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred!				1 test run
	chip_sw_rram_rma_unlocked	84740321741501981962232657196195981963143356119318582143619817589369653683733	337	UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	19008102439970556490790797527286170607250775042461563707813801706464988764671	404	UVM_INFO @ 6421.638928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	114755558706560090357602537432316032150629056992699916525044066757913729396316	380	UVM_ERROR @ 2992.254200 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 2992.254200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl				1 test run
	chip_sw_lc_ctrl_rand_to_scrap	40096159818169945178925618769297580097408424463892095736677931740064123549128	375	UVM_INFO @ 10702.815595 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:310)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	79118319435546849275305779097373859220602633809440351557777823835714096325177	371	UVM_INFO @ 3026.847804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	111739368904948746161878454972384731972926978756203207317456124384826589358381	373	UVM_INFO @ 2866.057561 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_hmac_multistream	66354843305369192709723659007919536257641175038770060590173640122834660162691	442	UVM_INFO @ 12010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.				1 test run
	chip_sw_clkmgr_reset_frequency	106632324161329262342029436970779269632116798133804187105827580041303639632176	400	UVM_INFO @ 10887.027468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	82212139528941226732156689609444102462262191395838968713620002677114145341605	407	UVM_INFO @ 3784.664328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts!				1 test run
	chip_jtag_csr_rw	95731509523512574291432375336894290238110414451930837021742448449147432923611	5365	UVM_INFO @ 2403.948660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)'				1 test run
	chip_sw_rv_dm_access_after_escalation_reset	115022262545141611755118654481897213561875993188318392816346213669447228260422	387	UVM_ERROR @ 3058.037160 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A UVM_INFO @ 3058.037160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:154) [chip_rv_dm_lc_disabled_vseq] Check failed rdata == exp_data (* [] vs []) RV_DM sbaddress read back check failed, got , expected				1 test run
	chip_rv_dm_lc_disabled	34920154573570351164309639069968357841003480086382888146015015238218841600600	323	UVM_INFO @ 8037.235803 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	84296112966824346236934763581995682993362171076752301098931834519620323661439	391	UVM_INFO @ 14637.127974 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	71318080730506183225937585989200860625106585742298963529329587487069724132760	339	UVM_INFO @ 10010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(reset_cause == HwReq)'				1 test run
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	1457538822454846779652414415992704651755307022901292652513083245748392259925	420	UVM_ERROR @ 3399.540495 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A UVM_INFO @ 3399.540495 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	67291530224308666758956687078803341901495049874511265408961482867408947541979	396	UVM_ERROR @ 2348.540449 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M UVM_INFO @ 2348.540449 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement				1 test run
	rom_raw_unlock	91624290835833135280051260860718863153250967788922055558241524736519465485074	398	UVM_INFO @ 18001.093171 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---