Simulation Results: clkmgr

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 91.83 %
  • code
  • 97.65 %
  • assert
  • 93.79 %
  • func
  • 84.05 %
  • line
  • 98.83 %
  • branch
  • 98.59 %
  • cond
  • 91.62 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.030s 16.557us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.220s 45.769us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.730s 227.331us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.730s 225.507us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.080s 16.709us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.600s 179.115us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.730s 227.331us 1 1 100.00
clkmgr_csr_aliasing 1.080s 16.709us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.220s 58.854us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.510s 74.657us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.160s 23.900us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.900s 13.276us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.030s 16.557us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 22.580s 2477.504us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 2.660s 266.150us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 22.580s 2477.504us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 2.080s 238.837us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.380s 71.187us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.570s 37.084us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.570s 37.084us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.220s 45.769us 1 1 100.00
clkmgr_csr_rw 1.730s 227.331us 1 1 100.00
clkmgr_csr_aliasing 1.080s 16.709us 1 1 100.00
clkmgr_same_csr_outstanding 1.900s 179.043us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.220s 45.769us 1 1 100.00
clkmgr_csr_rw 1.730s 227.331us 1 1 100.00
clkmgr_csr_aliasing 1.080s 16.709us 1 1 100.00
clkmgr_same_csr_outstanding 1.900s 179.043us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 1.380s 47.422us 0 1 0.00
clkmgr_tl_intg_err 2.220s 80.212us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 1015.060s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 1015.060s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 1015.060s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 1015.060s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 3.580s 455.822us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.220s 80.212us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 22.580s 2477.504us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 2.660s 266.150us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 1015.060s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.650s 116.680us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.390s 78.964us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.980s 31.484us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.820s 203.236us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.140s 52.762us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.730s 227.331us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.380s 47.422us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.730s 227.331us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.730s 227.331us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.380s 47.422us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.090s 235.518us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 17.220s 1547.767us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 104584830477065121124259682593346880782701184911760056323997770784947782757162 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 58817142329500904719698982259160498987389800091586870084978707603859729832456 105
UVM_INFO @ 47422006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---