Simulation Results: csrng

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.62 %
  • code
  • 92.32 %
  • assert
  • 93.23 %
  • func
  • 80.30 %
  • block
  • 97.05 %
  • line
  • 97.73 %
  • branch
  • 92.68 %
  • toggle
  • 93.17 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 48.800us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 54.560us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 62.101us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 59.000s 3788.153us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 22.751us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 4.000s 135.077us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 62.101us 1 1 100.00
csrng_csr_aliasing 2.000s 22.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 6.000s 269.196us 1 1 100.00
alerts 1 1 100.00
csrng_alert 10.000s 530.107us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 22.916us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 227.000s 15014.418us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 227.000s 15014.418us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 54.000s 1126.805us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 24.164us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 15.792us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 77.255us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 77.255us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 54.560us 1 1 100.00
csrng_csr_rw 3.000s 62.101us 1 1 100.00
csrng_csr_aliasing 2.000s 22.751us 1 1 100.00
csrng_same_csr_outstanding 2.000s 90.627us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 54.560us 1 1 100.00
csrng_csr_rw 3.000s 62.101us 1 1 100.00
csrng_csr_aliasing 2.000s 22.751us 1 1 100.00
csrng_same_csr_outstanding 2.000s 90.627us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 76.988us 1 1 100.00
csrng_tl_intg_err 3.000s 69.157us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 4.000s 136.045us 1 1 100.00
csrng_csr_rw 3.000s 62.101us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 10.000s 530.107us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 54.000s 1126.805us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 6.000s 269.196us 1 1 100.00
csrng_err 2.000s 22.916us 1 1 100.00
csrng_sec_cm 3.000s 76.988us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 6.000s 269.196us 1 1 100.00
csrng_err 2.000s 22.916us 1 1 100.00
csrng_sec_cm 3.000s 76.988us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 6.000s 269.196us 1 1 100.00
csrng_err 2.000s 22.916us 1 1 100.00
csrng_sec_cm 3.000s 76.988us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 6.000s 269.196us 1 1 100.00
csrng_err 2.000s 22.916us 1 1 100.00
csrng_sec_cm 3.000s 76.988us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 6.000s 269.196us 1 1 100.00
csrng_err 2.000s 22.916us 1 1 100.00
csrng_sec_cm 3.000s 76.988us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 10.000s 530.107us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 6.000s 269.196us 1 1 100.00
csrng_err 2.000s 22.916us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 54.000s 1126.805us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 10.000s 530.107us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 69.157us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 6.000s 269.196us 1 1 100.00
csrng_err 2.000s 22.916us 1 1 100.00
csrng_sec_cm 3.000s 76.988us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 6.000s 269.196us 1 1 100.00
csrng_err 2.000s 22.916us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 6.000s 269.196us 1 1 100.00
csrng_err 2.000s 22.916us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 6.000s 269.196us 1 1 100.00
csrng_err 2.000s 22.916us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 6.000s 269.196us 1 1 100.00
csrng_err 2.000s 22.916us 1 1 100.00
csrng_sec_cm 3.000s 76.988us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 6.000s 269.196us 1 1 100.00
csrng_err 2.000s 22.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 1.000s 3.574us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 1 test run
csrng_stress_all_with_rand_reset 71674881701556241773524291526860518425838473921631971662785174879763339770604 106
UVM_INFO @ 3574401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---