Simulation Results: edn/edn0

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 84.56 %
  • code
  • 78.86 %
  • assert
  • 95.44 %
  • func
  • 79.37 %
  • line
  • 96.58 %
  • branch
  • 88.15 %
  • cond
  • 83.75 %
  • toggle
  • 79.05 %
  • FSM
  • 46.77 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.430s 18.532us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.280s 50.456us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.120s 36.436us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 8.030s 324.826us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.340s 14.303us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.550s 23.549us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.120s 36.436us 1 1 100.00
edn_csr_aliasing 1.340s 14.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 3.560s 231.404us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 3.560s 231.404us 1 1 100.00
genbits 1 1 100.00
edn_genbits 3.560s 231.404us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.520s 21.388us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.420s 26.642us 1 1 100.00
errs 1 1 100.00
edn_err 1.250s 26.490us 1 1 100.00
disable 2 2 100.00
edn_disable 1.190s 23.492us 1 1 100.00
edn_disable_auto_req_mode 1.670s 51.733us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.360s 409.593us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.100s 28.705us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.380s 37.083us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.760s 37.935us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.760s 37.935us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.280s 50.456us 1 1 100.00
edn_csr_rw 1.120s 36.436us 1 1 100.00
edn_csr_aliasing 1.340s 14.303us 1 1 100.00
edn_same_csr_outstanding 1.460s 87.758us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.280s 50.456us 1 1 100.00
edn_csr_rw 1.120s 36.436us 1 1 100.00
edn_csr_aliasing 1.340s 14.303us 1 1 100.00
edn_same_csr_outstanding 1.460s 87.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.810s 3507.260us 1 1 100.00
edn_tl_intg_err 1.890s 82.861us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.400s 28.714us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.420s 26.642us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.810s 3507.260us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.810s 3507.260us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.810s 3507.260us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.810s 3507.260us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.420s 26.642us 1 1 100.00
edn_sec_cm 5.810s 3507.260us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.420s 26.642us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.890s 82.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 65.380s 3282.511us 1 1 100.00