Simulation Results: edn/edn1

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 86.44 %
  • code
  • 84.23 %
  • assert
  • 97.14 %
  • func
  • 77.94 %
  • line
  • 98.03 %
  • branch
  • 93.07 %
  • cond
  • 88.54 %
  • toggle
  • 94.93 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.220s 145.121us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.230s 36.429us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.050s 27.121us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.840s 652.667us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.240s 63.626us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.370s 32.181us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.050s 27.121us 1 1 100.00
edn_csr_aliasing 1.240s 63.626us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.540s 36.959us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.540s 36.959us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.540s 36.959us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.440s 23.248us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.530s 94.772us 1 1 100.00
errs 1 1 100.00
edn_err 1.360s 24.736us 1 1 100.00
disable 2 2 100.00
edn_disable 1.160s 36.912us 1 1 100.00
edn_disable_auto_req_mode 1.490s 53.837us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.160s 82.617us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.090s 22.666us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.250s 20.892us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.290s 60.225us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.290s 60.225us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.230s 36.429us 1 1 100.00
edn_csr_rw 1.050s 27.121us 1 1 100.00
edn_csr_aliasing 1.240s 63.626us 1 1 100.00
edn_same_csr_outstanding 1.440s 25.528us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.230s 36.429us 1 1 100.00
edn_csr_rw 1.050s 27.121us 1 1 100.00
edn_csr_aliasing 1.240s 63.626us 1 1 100.00
edn_same_csr_outstanding 1.440s 25.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.210s 357.020us 1 1 100.00
edn_tl_intg_err 2.430s 144.073us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.180s 16.120us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.530s 94.772us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.210s 357.020us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.210s 357.020us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.210s 357.020us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.210s 357.020us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.530s 94.772us 1 1 100.00
edn_sec_cm 6.210s 357.020us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.530s 94.772us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.430s 144.073us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 42.820s 1909.237us 1 1 100.00