Simulation Results: hmac

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 75.25 %
  • code
  • 86.39 %
  • assert
  • 97.38 %
  • func
  • 41.98 %
  • line
  • 99.54 %
  • branch
  • 99.02 %
  • cond
  • 96.02 %
  • toggle
  • 46.17 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 15.850s 916.242us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.030s 17.613us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.980s 45.498us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.170s 166.168us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.600s 206.109us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.460s 33.610us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.980s 45.498us 1 1 100.00
hmac_csr_aliasing 1.600s 206.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 116.070s 48630.022us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 52.320s 1482.960us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 13.140s 1983.361us 1 1 100.00
hmac_test_sha384_vectors 30.440s 1378.175us 1 1 100.00
hmac_test_sha512_vectors 422.440s 85876.966us 1 1 100.00
hmac_test_hmac256_vectors 10.400s 279.795us 1 1 100.00
hmac_test_hmac384_vectors 8.640s 922.837us 1 1 100.00
hmac_test_hmac512_vectors 14.740s 321.109us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 25.360s 782.718us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 37.570s 964.396us 1 1 100.00
error 1 1 100.00
hmac_error 73.260s 2082.048us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 76.820s 30991.645us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 15.850s 916.242us 1 1 100.00
hmac_long_msg 116.070s 48630.022us 1 1 100.00
hmac_back_pressure 52.320s 1482.960us 1 1 100.00
hmac_datapath_stress 37.570s 964.396us 1 1 100.00
hmac_burst_wr 25.360s 782.718us 1 1 100.00
hmac_stress_all 6.390s 176.527us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 15.850s 916.242us 1 1 100.00
hmac_long_msg 116.070s 48630.022us 1 1 100.00
hmac_back_pressure 52.320s 1482.960us 1 1 100.00
hmac_datapath_stress 37.570s 964.396us 1 1 100.00
hmac_wipe_secret 76.820s 30991.645us 1 1 100.00
hmac_test_sha256_vectors 13.140s 1983.361us 1 1 100.00
hmac_test_sha384_vectors 30.440s 1378.175us 1 1 100.00
hmac_test_sha512_vectors 422.440s 85876.966us 1 1 100.00
hmac_test_hmac256_vectors 10.400s 279.795us 1 1 100.00
hmac_test_hmac384_vectors 8.640s 922.837us 1 1 100.00
hmac_test_hmac512_vectors 14.740s 321.109us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 15.850s 916.242us 1 1 100.00
hmac_long_msg 116.070s 48630.022us 1 1 100.00
hmac_back_pressure 52.320s 1482.960us 1 1 100.00
hmac_datapath_stress 37.570s 964.396us 1 1 100.00
hmac_burst_wr 25.360s 782.718us 1 1 100.00
hmac_error 73.260s 2082.048us 1 1 100.00
hmac_wipe_secret 76.820s 30991.645us 1 1 100.00
hmac_test_sha256_vectors 13.140s 1983.361us 1 1 100.00
hmac_test_sha384_vectors 30.440s 1378.175us 1 1 100.00
hmac_test_sha512_vectors 422.440s 85876.966us 1 1 100.00
hmac_test_hmac256_vectors 10.400s 279.795us 1 1 100.00
hmac_test_hmac384_vectors 8.640s 922.837us 1 1 100.00
hmac_test_hmac512_vectors 14.740s 321.109us 1 1 100.00
hmac_stress_all 6.390s 176.527us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 6.390s 176.527us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.850s 47.307us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.920s 166.193us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.350s 232.785us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.350s 232.785us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.030s 17.613us 1 1 100.00
hmac_csr_rw 0.980s 45.498us 1 1 100.00
hmac_csr_aliasing 1.600s 206.109us 1 1 100.00
hmac_same_csr_outstanding 1.500s 103.393us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.030s 17.613us 1 1 100.00
hmac_csr_rw 0.980s 45.498us 1 1 100.00
hmac_csr_aliasing 1.600s 206.109us 1 1 100.00
hmac_same_csr_outstanding 1.500s 103.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.030s 37.002us 1 1 100.00
hmac_tl_intg_err 2.170s 171.196us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.170s 171.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 15.850s 916.242us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.120s 1104.126us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 61.600s 12797.018us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 6.060s 356.991us 1 1 100.00