Simulation Results: keymgr_dpe/earlgrey

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 64.85 %
  • code
  • 82.24 %
  • assert
  • 97.44 %
  • func
  • 14.88 %
  • line
  • 97.35 %
  • branch
  • 93.77 %
  • cond
  • 86.29 %
  • toggle
  • 58.10 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_dpe_smoke 18.030s 3801.749us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 1.130s 22.386us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 0.970s 17.271us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 4.120s 131.236us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 1.380s 75.143us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.530s 565.879us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 0.970s 17.271us 1 1 100.00
keymgr_dpe_csr_aliasing 1.380s 75.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 0.940s 18.503us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 1.110s 16.719us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 1.950s 158.662us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 1.950s 158.662us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.130s 22.386us 1 1 100.00
keymgr_dpe_csr_rw 0.970s 17.271us 1 1 100.00
keymgr_dpe_csr_aliasing 1.380s 75.143us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.970s 215.039us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.130s 22.386us 1 1 100.00
keymgr_dpe_csr_rw 0.970s 17.271us 1 1 100.00
keymgr_dpe_csr_aliasing 1.380s 75.143us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.970s 215.039us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 12.000s 1469.962us 1 1 100.00
keymgr_dpe_tl_intg_err 2.860s 449.997us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.920s 7.325us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.920s 7.325us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.920s 7.325us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.920s 7.325us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 3.610s 203.791us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 12.000s 1469.962us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 12.000s 1469.962us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(reg2hw.control_shadowed.slot_dst_sel.q < NumInstHwSlot)' 2 test runs
keymgr_dpe_shadow_reg_errors 50953818580104051115617056237450337161898835089184005823465257605728123711199 83
UVM_ERROR @ 7324510 ps: (keymgr_dpe.sv:321) [ASSERT FAILED] DstSelInRange_A
UVM_INFO @ 7324510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_dpe_shadow_reg_errors_with_csr_rw 35476572035032336870552146284559479004827109901707889722968117423430043182130 84
UVM_ERROR @ 203791489 ps: (keymgr_dpe.sv:321) [ASSERT FAILED] DstSelInRange_A
UVM_INFO @ 203791489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---