Simulation Results: lc_ctrl/volatile_unlock_disabled

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.12 %
  • code
  • 83.53 %
  • assert
  • 94.55 %
  • func
  • 92.29 %
  • line
  • 97.20 %
  • branch
  • 93.76 %
  • cond
  • 79.24 %
  • toggle
  • 84.85 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.370s 41.833us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.210s 111.772us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.170s 26.313us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.970s 129.930us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 14.586us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.290s 35.982us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.170s 26.313us 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 14.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.220s 46.254us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.210s 214.923us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.100s 64.637us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.540s 96.366us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.600s 767.913us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.480s 1695.640us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.600s 767.913us 1 1 100.00
lc_ctrl_prog_failure 2.540s 96.366us 1 1 100.00
lc_ctrl_errors 7.480s 1695.640us 1 1 100.00
lc_ctrl_security_escalation 4.650s 1274.958us 1 1 100.00
lc_ctrl_jtag_state_failure 25.310s 5686.109us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.730s 2213.935us 1 1 100.00
lc_ctrl_jtag_errors 28.340s 6860.330us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.980s 388.595us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.860s 701.910us 1 1 100.00
lc_ctrl_jtag_prog_failure 8.730s 2213.935us 1 1 100.00
lc_ctrl_jtag_errors 28.340s 6860.330us 1 1 100.00
lc_ctrl_jtag_access 4.110s 1512.230us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.330s 1429.538us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.050s 521.915us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.860s 84.861us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.240s 3045.168us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.400s 381.567us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.270s 16.911us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.810s 112.295us 1 1 100.00
lc_ctrl_jtag_alert_test 1.310s 30.126us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 10.870s 1835.273us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.110s 98.166us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 52.300s 2902.845us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.020s 28.546us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.830s 26.186us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.830s 26.186us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.210s 111.772us 1 1 100.00
lc_ctrl_csr_rw 1.170s 26.313us 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 14.586us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.250s 31.547us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.210s 111.772us 1 1 100.00
lc_ctrl_csr_rw 1.170s 26.313us 1 1 100.00
lc_ctrl_csr_aliasing 1.280s 14.586us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.250s 31.547us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.800s 226.725us 1 1 100.00
lc_ctrl_tl_intg_err 1.830s 69.943us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.830s 69.943us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.210s 214.923us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 767.913us 1 1 100.00
lc_ctrl_sec_cm 7.800s 226.725us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 767.913us 1 1 100.00
lc_ctrl_sec_cm 7.800s 226.725us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.600s 767.913us 1 1 100.00
lc_ctrl_sec_cm 7.800s 226.725us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.600s 767.913us 1 1 100.00
lc_ctrl_sec_cm 7.800s 226.725us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 767.913us 1 1 100.00
lc_ctrl_sec_cm 7.800s 226.725us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 767.913us 1 1 100.00
lc_ctrl_sec_cm 7.800s 226.725us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 767.913us 1 1 100.00
lc_ctrl_sec_cm 7.800s 226.725us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.600s 767.913us 1 1 100.00
lc_ctrl_sec_cm 7.800s 226.725us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.650s 1274.958us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.220s 46.254us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.860s 701.910us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.020s 449.998us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.020s 449.998us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.660s 383.828us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.130s 469.885us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.130s 469.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 39.520s 6406.764us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 81964140329984595635044452372174897162706865810792441714159807381607037957570 7541
UVM_INFO @ 6406763556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---