Simulation Results: lc_ctrl/volatile_unlock_enabled

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.54 %
  • code
  • 84.13 %
  • assert
  • 94.13 %
  • func
  • 93.37 %
  • line
  • 97.26 %
  • branch
  • 93.86 %
  • cond
  • 79.77 %
  • toggle
  • 85.27 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.050s 43.200us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.150s 29.495us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.150s 41.022us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.970s 236.225us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 98.295us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.100s 57.308us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.150s 41.022us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 98.295us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 7.780s 59.919us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.750s 1155.487us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.930s 12.954us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.840s 102.832us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 11.570s 368.743us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.930s 486.255us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 11.570s 368.743us 1 1 100.00
lc_ctrl_prog_failure 2.840s 102.832us 1 1 100.00
lc_ctrl_errors 5.930s 486.255us 1 1 100.00
lc_ctrl_security_escalation 5.810s 555.424us 1 1 100.00
lc_ctrl_jtag_state_failure 25.480s 8735.787us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.390s 257.134us 1 1 100.00
lc_ctrl_jtag_errors 26.810s 2233.789us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.230s 1178.877us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.660s 547.287us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.390s 257.134us 1 1 100.00
lc_ctrl_jtag_errors 26.810s 2233.789us 1 1 100.00
lc_ctrl_jtag_access 7.280s 483.522us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.250s 813.992us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.240s 174.646us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.280s 34.418us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.020s 1287.509us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 1.640s 70.801us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.470s 249.974us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.290s 66.305us 1 1 100.00
lc_ctrl_jtag_alert_test 1.430s 84.961us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 12.310s 14517.167us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.110s 16.417us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 36.790s 6766.704us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.100s 52.660us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.410s 338.258us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.410s 338.258us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.150s 29.495us 1 1 100.00
lc_ctrl_csr_rw 1.150s 41.022us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 98.295us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.930s 94.442us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.150s 29.495us 1 1 100.00
lc_ctrl_csr_rw 1.150s 41.022us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 98.295us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.930s 94.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.160s 232.409us 1 1 100.00
lc_ctrl_tl_intg_err 3.580s 938.283us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.580s 938.283us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.750s 1155.487us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 11.570s 368.743us 1 1 100.00
lc_ctrl_sec_cm 7.160s 232.409us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 11.570s 368.743us 1 1 100.00
lc_ctrl_sec_cm 7.160s 232.409us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.570s 368.743us 1 1 100.00
lc_ctrl_sec_cm 7.160s 232.409us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.570s 368.743us 1 1 100.00
lc_ctrl_sec_cm 7.160s 232.409us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 11.570s 368.743us 1 1 100.00
lc_ctrl_sec_cm 7.160s 232.409us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.570s 368.743us 1 1 100.00
lc_ctrl_sec_cm 7.160s 232.409us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.570s 368.743us 1 1 100.00
lc_ctrl_sec_cm 7.160s 232.409us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 11.570s 368.743us 1 1 100.00
lc_ctrl_sec_cm 7.160s 232.409us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.810s 555.424us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 7.780s 59.919us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.660s 547.287us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.540s 484.039us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.540s 484.039us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.540s 1152.485us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.580s 865.887us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.580s 865.887us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 41.040s 5858.823us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 79609999235324082803316234694740997765704771705793794360934718889847832275465 4394
UVM_INFO @ 5858823269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---