Simulation Results: otbn

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.79 %
  • code
  • 86.17 %
  • assert
  • 90.06 %
  • func
  • 99.15 %
  • block
  • 99.22 %
  • line
  • 99.44 %
  • branch
  • 94.43 %
  • toggle
  • 84.61 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 12.000s 76.906us 1 1 100.00
otbn_smoke_vectorized 11.000s 570.120us 1 1 100.00
single_binary 1 1 100.00
otbn_single 11.000s 51.762us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 6.000s 53.128us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 42.708us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 8.000s 158.793us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 6.000s 22.829us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 68.531us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 42.708us 1 1 100.00
otbn_csr_aliasing 6.000s 22.829us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 196.000s 27833.461us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 35.000s 594.077us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 51.000s 468.271us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 90.000s 971.487us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 102.000s 323.426us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 70.000s 609.705us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 12.000s 75.006us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 36.816us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 31.000s 107.855us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 7.000s 41.886us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 7.000s 20.077us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 11.000s 125.435us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 11.000s 125.435us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 6.000s 53.128us 1 1 100.00
otbn_csr_rw 5.000s 42.708us 1 1 100.00
otbn_csr_aliasing 6.000s 22.829us 1 1 100.00
otbn_same_csr_outstanding 6.000s 26.682us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 6.000s 53.128us 1 1 100.00
otbn_csr_rw 5.000s 42.708us 1 1 100.00
otbn_csr_aliasing 6.000s 22.829us 1 1 100.00
otbn_same_csr_outstanding 6.000s 26.682us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 10.000s 47.198us 1 1 100.00
otbn_dmem_err 13.000s 64.775us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 16.000s 60.536us 1 1 100.00
otbn_controller_ispr_rdata_err 10.000s 18.037us 1 1 100.00
otbn_mac_bignum_acc_err 11.000s 54.173us 1 1 100.00
otbn_urnd_err 7.000s 10.184us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 7.000s 16.767us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 12.000s 38.272us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 8.000s 74.031us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
otbn_tl_intg_err 42.000s 212.846us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 68.000s 181.595us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 12.000s 76.906us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 13.000s 64.775us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 10.000s 47.198us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 42.000s 212.846us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 12.000s 75.006us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 47.198us 1 1 100.00
otbn_dmem_err 13.000s 64.775us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 36.816us 1 1 100.00
otbn_illegal_mem_acc 7.000s 16.767us 1 1 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 11.000s 51.762us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 47.198us 1 1 100.00
otbn_dmem_err 13.000s 64.775us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 36.816us 1 1 100.00
otbn_illegal_mem_acc 7.000s 16.767us 1 1 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 12.000s 75.006us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 47.198us 1 1 100.00
otbn_dmem_err 13.000s 64.775us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 36.816us 1 1 100.00
otbn_illegal_mem_acc 7.000s 16.767us 1 1 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 11.000s 51.762us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 39.470us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 10.000s 70.244us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 27.000s 256.761us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 27.000s 256.761us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 10.000s 14.361us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 105.172us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 34.000s 176.467us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 34.000s 176.467us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 110.812us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 51.762us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 51.762us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 11.000s 51.762us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 102.000s 323.426us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 11.000s 51.762us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 11.000s 51.762us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 12.000s 27.810us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 11.000s 51.762us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 369.000s 29100.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 57.000s 135.917us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:349) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 50115933901242572778748040463699401788777375433796471602307567576933673939335 197
UVM_INFO @ 135917035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---