Simulation Results: otp_ctrl

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 79.91 %
  • code
  • 76.41 %
  • assert
  • 94.06 %
  • func
  • 69.27 %
  • line
  • 88.52 %
  • branch
  • 83.36 %
  • cond
  • 89.98 %
  • toggle
  • 77.32 %
  • FSM
  • 42.88 %
Validation stages
V1
100.00%
V2
90.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.800s 201.663us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 8.410s 941.297us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.560s 69.092us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.980s 89.457us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 8.130s 617.321us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.750s 920.773us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.840s 79.680us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.980s 89.457us 1 1 100.00
otp_ctrl_csr_aliasing 2.750s 920.773us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.600s 71.856us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.510s 64.086us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 21.580s 6015.378us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 7.620s 569.201us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 9.400s 943.177us 1 1 100.00
otp_ctrl_check_fail 28.750s 11244.270us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.270s 125.937us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 10.750s 532.381us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 30.930s 8353.326us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 13.960s 540.579us 1 1 100.00
otp_ctrl_parallel_lc_esc 7.550s 2098.411us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 13.520s 645.121us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 15.040s 502.516us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 10.710s 1435.972us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 7.280s 710.294us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.570s 81.940us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.260s 75.765us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.760s 1371.988us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.760s 1371.988us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.560s 69.092us 1 1 100.00
otp_ctrl_csr_rw 1.980s 89.457us 1 1 100.00
otp_ctrl_csr_aliasing 2.750s 920.773us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.640s 110.802us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.560s 69.092us 1 1 100.00
otp_ctrl_csr_rw 1.980s 89.457us 1 1 100.00
otp_ctrl_csr_aliasing 2.750s 920.773us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.640s 110.802us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
otp_ctrl_tl_intg_err 12.620s 2505.764us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.620s 2505.764us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 8.410s 941.297us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 8.410s 941.297us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.550s 2098.411us 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.550s 2098.411us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.550s 2098.411us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.550s 2098.411us 1 1 100.00
otp_ctrl_macro_errs 15.040s 502.516us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.550s 2098.411us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.550s 2098.411us 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.550s 2098.411us 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.550s 2098.411us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.550s 2098.411us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 7.550s 2098.411us 1 1 100.00
otp_ctrl_macro_errs 15.040s 502.516us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.550s 2098.411us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.550s 2098.411us 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 7.620s 569.201us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 28.750s 11244.270us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 10.750s 532.381us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 10.750s 532.381us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 10.750s 532.381us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 10.750s 532.381us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 10.750s 532.381us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 8.410s 941.297us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 10.750s 532.381us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 8.410s 941.297us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.640s 10376.262us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.270s 125.937us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 8.410s 941.297us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 8.410s 941.297us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 15.040s 502.516us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 13.800s 3971.249us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 5.550s 666.115us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_macro_errs 33727192260458930132735250729182736375080528788490398458579480504571216278907 10390
UVM_INFO @ 502515880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 3935934030459153521728914690398403423671400375842003013475093737110905190645 669
UVM_INFO @ 666115245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1306) scoreboard [scoreboard] pwr_otp_idle output is * while expect * within * cycles 1 test run
otp_ctrl_stress_all 44841131634276506357701079816019927029618626780046860257837014219347186433752 2497
UVM_INFO @ 710294085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---