Simulation Results: pwrmgr

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 94.00 %
  • code
  • 89.93 %
  • assert
  • 96.34 %
  • func
  • 95.72 %
  • line
  • 98.93 %
  • branch
  • 95.62 %
  • cond
  • 93.07 %
  • toggle
  • 90.02 %
  • FSM
  • 72.00 %
Validation stages
V1
100.00%
V2
80.00%
V2S
72.73%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.810s 30.656us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.900s 34.644us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.830s 28.432us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.290s 654.783us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.890s 34.971us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.890s 41.884us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.830s 28.432us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 34.971us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.680s 28.041us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.680s 28.041us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.880s 252.972us 1 1 100.00
pwrmgr_lowpower_invalid 0.910s 85.403us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.830s 99.100us 1 1 100.00
pwrmgr_reset_invalid 0.790s 219.311us 0 1 0.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.830s 99.100us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.890s 211.686us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.970s 129.776us 1 1 100.00
disable_rom_integrity_check 0 1 0.00
pwrmgr_disable_rom_integrity_check 1.930s 1000.000us 0 1 0.00
stress_all 0 1 0.00
pwrmgr_stress_all 10800.033s 0.000us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.920s 19.212us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.820s 77.759us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.820s 77.759us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.900s 34.644us 1 1 100.00
pwrmgr_csr_rw 0.830s 28.432us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 34.971us 1 1 100.00
pwrmgr_same_csr_outstanding 0.880s 154.706us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.900s 34.644us 1 1 100.00
pwrmgr_csr_rw 0.830s 28.432us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 34.971us 1 1 100.00
pwrmgr_same_csr_outstanding 0.880s 154.706us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 3600.034s 0.000us 0 1 0.00
pwrmgr_sec_cm 3600.038s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 3600.038s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 3600.038s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.034s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.670s 1210.274us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.890s 211.686us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.720s 3598.579us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.990s 170.557us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.790s 98.745us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 3600.038s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 3600.038s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 3600.038s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.910s 51.753us 1 1 100.00
sec_cm_main_pd_rst_local_esc 0 1 0.00
pwrmgr_glitch 3600.039s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.960s 214.311us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.830s 28.432us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.830s 28.432us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 1.170s 1098.237us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3600.023s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 5 test runs
pwrmgr_glitch 81999959751788239906440166247404710615814915159252959692855009433934484734753 None
pwrmgr_tl_intg_err 920715173973630005743670124523311528778616401128841798171223937002881224586 None
pwrmgr_sec_cm 26799151909381937886193961948039144380007378593654459876420041174545342460455 None
pwrmgr_stress_all_with_rand_reset 62027496241552522671640302580839402109957247669836857582097119874356882041534 None
pwrmgr_stress_all 111246101770711768165617759985754601020251285480699701161321750689331103250398 None
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_disable_rom_integrity_check 28839114597297586709554239435686285660839396427905053124554563701352686763235 109
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLcInit 1 test run
pwrmgr_reset_invalid 32880496482788321156164388359289254198495446557214190431796127641386536130011 106
UVM_INFO @ 219311180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---