Simulation Results: rom_ctrl/192kb

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 94.42 %
  • code
  • 91.20 %
  • assert
  • 97.10 %
  • func
  • 94.96 %
  • line
  • 98.82 %
  • branch
  • 97.83 %
  • cond
  • 97.33 %
  • toggle
  • 95.34 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 19.350s 1076.241us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 20.950s 125.148us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 10.570s 57.680us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 12.080s 154.127us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 10.910s 53.110us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.620s 60.522us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 10.570s 57.680us 1 1 100.00
rom_ctrl_csr_aliasing 10.910s 53.110us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 14.430s 73.787us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 12.510s 84.213us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 10.320s 9.404us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 81.030s 3157.367us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 19.650s 64.705us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 10.920s 59.495us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 12.170s 176.527us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 12.170s 176.527us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 20.950s 125.148us 1 1 100.00
rom_ctrl_csr_rw 10.570s 57.680us 1 1 100.00
rom_ctrl_csr_aliasing 10.910s 53.110us 1 1 100.00
rom_ctrl_same_csr_outstanding 12.000s 54.746us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 20.950s 125.148us 1 1 100.00
rom_ctrl_csr_rw 10.570s 57.680us 1 1 100.00
rom_ctrl_csr_aliasing 10.910s 53.110us 1 1 100.00
rom_ctrl_same_csr_outstanding 12.000s 54.746us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.660s 41171.483us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 37.900s 151.059us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 864.350s 929.057us 1 1 100.00
rom_ctrl_tl_intg_err 366.980s 2032.273us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 864.350s 929.057us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 864.350s 929.057us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.660s 41171.483us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.660s 41171.483us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.660s 41171.483us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.660s 41171.483us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.660s 41171.483us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 864.350s 929.057us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 864.350s 929.057us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 19.350s 1076.241us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 19.350s 1076.241us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 19.350s 1076.241us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 366.980s 2032.273us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.660s 41171.483us 1 1 100.00
rom_ctrl_kmac_err_chk 19.650s 64.705us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.660s 41171.483us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.660s 41171.483us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 279.660s 41171.483us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 37.900s 151.059us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 864.350s 929.057us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 53.450s 52124.670us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 87586727839023836200062414955596177329408049628243093325805629945901071197276 85
UVM_INFO @ 9403802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---