Simulation Results: rstmgr

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 98.29 %
  • code
  • 99.42 %
  • assert
  • 98.66 %
  • func
  • 96.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.03 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.350s 284.648us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.160s 120.276us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.240s 95.737us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.860s 384.368us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.240s 70.984us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.130s 196.986us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.240s 95.737us 1 1 100.00
rstmgr_csr_aliasing 1.240s 70.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.070s 150.957us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.500s 183.494us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.770s 75.649us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.770s 1077.422us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.770s 1077.422us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.770s 1077.422us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.770s 1077.422us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 41.500s 15101.445us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.070s 95.651us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.150s 419.112us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.150s 419.112us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.160s 120.276us 1 1 100.00
rstmgr_csr_rw 1.240s 95.737us 1 1 100.00
rstmgr_csr_aliasing 1.240s 70.984us 1 1 100.00
rstmgr_same_csr_outstanding 1.180s 77.190us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.160s 120.276us 1 1 100.00
rstmgr_csr_rw 1.240s 95.737us 1 1 100.00
rstmgr_csr_aliasing 1.240s 70.984us 1 1 100.00
rstmgr_same_csr_outstanding 1.180s 77.190us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 29.590s 16815.575us 1 1 100.00
rstmgr_tl_intg_err 2.300s 846.074us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 29.590s 16815.575us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 29.590s 16815.575us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.300s 846.074us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.920s 117.487us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.310s 2826.094us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.170s 302.114us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 29.590s 16815.575us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.240s 95.737us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.240s 95.737us 1 1 100.00