Simulation Results: rv_timer

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.28 %
  • code
  • 94.66 %
  • assert
  • 96.82 %
  • func
  • 97.35 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.650s 153.907us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.570s 23.755us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.700s 32.352us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.470s 247.706us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.600s 14.366us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.650s 38.572us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.700s 32.352us 1 1 100.00
rv_timer_csr_aliasing 0.600s 14.366us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.650s 55.818us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 0.950s 3561.271us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 10.710s 9206.817us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 10.710s 9206.817us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 4.410s 5277.237us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.660s 43.203us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.660s 29.715us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.960s 601.079us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.960s 601.079us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.570s 23.755us 1 1 100.00
rv_timer_csr_rw 0.700s 32.352us 1 1 100.00
rv_timer_csr_aliasing 0.600s 14.366us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 52.489us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.570s 23.755us 1 1 100.00
rv_timer_csr_rw 0.700s 32.352us 1 1 100.00
rv_timer_csr_aliasing 0.600s 14.366us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 52.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.930s 72.051us 1 1 100.00
rv_timer_tl_intg_err 0.980s 384.330us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.980s 384.330us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.650s 237.377us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.970s 565.297us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 31.090s 9846.123us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 115441765680783034472606730752034081838136793667406053793905772868273544314339 84
UVM_INFO @ 237376931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 34134931865698547877747015720092974523673717865285427085172695718149597123412 82
UVM_INFO @ 565297168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---