Simulation Results: spi_device/1r1w

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 83.64 %
  • code
  • 91.37 %
  • assert
  • 95.40 %
  • func
  • 64.14 %
  • line
  • 98.85 %
  • branch
  • 98.15 %
  • cond
  • 96.21 %
  • toggle
  • 74.30 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 17.590s 2582.720us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.960s 25.600us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.070s 125.249us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 24.030s 1694.700us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 1.920s 47.533us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.720s 139.090us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.070s 125.249us 1 1 100.00
spi_device_csr_aliasing 1.920s 47.533us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.680s 22.976us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.510s 66.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.850s 20.692us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.700s 1.215us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.830s 5.957us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.580s 113.312us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.580s 113.312us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 8.370s 18182.124us 1 1 100.00
spi_device_tpm_sts_read 1.110s 272.579us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 4.860s 393.421us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.770s 33.716us 1 1 100.00
spi_device_flash_all 14.120s 13729.868us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.320s 1120.020us 1 1 100.00
spi_device_flash_all 14.120s 13729.868us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.320s 1120.020us 1 1 100.00
spi_device_flash_all 14.120s 13729.868us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 14.120s 13729.868us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.410s 333.018us 1 1 100.00
spi_device_flash_all 14.120s 13729.868us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.410s 333.018us 1 1 100.00
spi_device_flash_all 14.120s 13729.868us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.410s 333.018us 1 1 100.00
spi_device_flash_all 14.120s 13729.868us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.410s 333.018us 1 1 100.00
spi_device_flash_all 14.120s 13729.868us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.410s 333.018us 1 1 100.00
spi_device_flash_all 14.120s 13729.868us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.700s 695.311us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 27.540s 6397.028us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 27.540s 6397.028us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 27.540s 6397.028us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.550s 69.573us 1 1 100.00
spi_device_read_buffer_direct 2.480s 273.729us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 27.540s 6397.028us 1 1 100.00
spi_device_flash_all 14.120s 13729.868us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 14.120s 13729.868us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 14.120s 13729.868us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.830s 284.083us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.830s 284.083us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 96.790s 176359.587us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 17.590s 2582.720us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 60.410s 23369.584us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 88.870s 17867.893us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.680s 19.795us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.810s 25.538us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.180s 3222.597us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.180s 3222.597us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.960s 25.600us 1 1 100.00
spi_device_csr_rw 1.070s 125.249us 1 1 100.00
spi_device_csr_aliasing 1.920s 47.533us 1 1 100.00
spi_device_same_csr_outstanding 2.260s 156.733us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.960s 25.600us 1 1 100.00
spi_device_csr_rw 1.070s 125.249us 1 1 100.00
spi_device_csr_aliasing 1.920s 47.533us 1 1 100.00
spi_device_same_csr_outstanding 2.260s 156.733us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.100s 121.687us 1 1 100.00
spi_device_tl_intg_err 3.980s 99.951us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 3.980s 99.951us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 59203986399696968228476662129082282659825320277070598560124657472909239965790 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1058750 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1058750 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[988])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 106895788674809347670183469662289520401495886321669558990571126598355960577194 76
UVM_ERROR @ 3483419 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x46 [1000110] vs 0x0 [0])
UVM_ERROR @ 3512419 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2d5 [1011010101] vs 0x0 [0])
UVM_ERROR @ 3519419 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x36d [1101101101] vs 0x0 [0])
UVM_ERROR @ 3534419 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x32e [1100101110] vs 0x0 [0])