Simulation Results: sram_ctrl/main

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.21 %
  • code
  • 93.62 %
  • assert
  • 97.01 %
  • func
  • 95.00 %
  • block
  • 92.66 %
  • line
  • 93.64 %
  • branch
  • 89.29 %
  • toggle
  • 91.56 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 343.625us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 40.855us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.884us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 162.850us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 71.573us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 1440.224us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 25.884us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 71.573us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 248.000s 45407.067us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 68.000s 5101.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 21.000s 5455.567us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 125.000s 22074.894us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 208.000s 15311.188us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 72.000s 23771.883us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 57.000s 47868.746us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 51.000s 39894.545us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 7.000s 13980.941us 1 1 100.00
sram_ctrl_partial_access_b2b 294.000s 22420.009us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.000s 1394.963us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.000s 691.893us 1 1 100.00
sram_ctrl_throughput_w_readback 7.000s 1356.604us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 22.000s 10178.242us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 2236.268us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 410.000s 79517.124us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 12.636us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 501.489us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 501.489us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 40.855us 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.884us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 71.573us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 52.545us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 40.855us 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.884us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 71.573us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 52.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 7185.998us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1293.159us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 166.692us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1293.159us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 166.692us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 22.000s 10178.242us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 22.000s 10178.242us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.884us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 51.000s 39894.545us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 51.000s 39894.545us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 51.000s 39894.545us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 57.000s 47868.746us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3602.118s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 23.000s 7185.998us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3602.104s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 343.625us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 343.625us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 51.000s 39894.545us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1293.159us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 57.000s 47868.746us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1293.159us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1293.159us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 343.625us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1293.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 9.000s 947.934us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 86418539597183199544687288132387278972651448015824903796400352249513888874110 None
sram_ctrl_mubi_enc_err 103005595906109678752515662261580620537602634105506954571585911771314973516067 None