| V1 |
|
100.00% |
| V2 |
|
94.44% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| sysrst_ctrl_smoke | 1.250s | 2163.516us | 1 | 1 | 100.00 | |
| input_output_inverted | 1 | 1 | 100.00 | |||
| sysrst_ctrl_in_out_inverted | 5.030s | 2443.711us | 1 | 1 | 100.00 | |
| combo_detect_ec_rst | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect_ec_rst | 3.270s | 2228.877us | 1 | 1 | 100.00 | |
| combo_detect_ec_rst_with_pre_cond | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 1.770s | 2290.258us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 4.440s | 6047.881us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_rw | 1.870s | 2079.605us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_bit_bash | 149.990s | 76049.982us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_aliasing | 1.710s | 2337.167us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_mem_rw_with_rand_reset | 1.190s | 2192.206us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| sysrst_ctrl_csr_rw | 1.870s | 2079.605us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 1.710s | 2337.167us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| combo_detect | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect | 41.910s | 98119.279us | 1 | 1 | 100.00 | |
| combo_detect_with_pre_cond | 0 | 1 | 0.00 | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 88.010s | 46613.781us | 0 | 1 | 0.00 | |
| auto_block_key_outputs | 1 | 1 | 100.00 | |||
| sysrst_ctrl_auto_blk_key_output | 2.430s | 3398.116us | 1 | 1 | 100.00 | |
| keyboard_input_triggered_interrupt | 1 | 1 | 100.00 | |||
| sysrst_ctrl_edge_detect | 2.770s | 2576.717us | 1 | 1 | 100.00 | |
| pin_output_keyboard_inversion_control | 1 | 1 | 100.00 | |||
| sysrst_ctrl_pin_override_test | 4.740s | 2509.815us | 1 | 1 | 100.00 | |
| pin_input_value_accessibility | 1 | 1 | 100.00 | |||
| sysrst_ctrl_pin_access_test | 1.650s | 2142.421us | 1 | 1 | 100.00 | |
| ec_power_on_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_ec_pwr_on_rst | 3.870s | 3189.322us | 1 | 1 | 100.00 | |
| flash_write_protect_output | 1 | 1 | 100.00 | |||
| sysrst_ctrl_flash_wr_prot_out | 1.510s | 2633.205us | 1 | 1 | 100.00 | |
| ultra_low_power_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_ultra_low_pwr | 219.290s | 1687807.259us | 1 | 1 | 100.00 | |
| sysrst_ctrl_feature_disable | 1 | 1 | 100.00 | |||
| sysrst_ctrl_feature_disable | 21.120s | 37814.958us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| sysrst_ctrl_stress_all | 121.250s | 230327.546us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_alert_test | 1.920s | 2023.616us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_intr_test | 2.460s | 2019.406us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_errors | 4.930s | 2044.887us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_errors | 4.930s | 2044.887us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 4.440s | 6047.881us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_rw | 1.870s | 2079.605us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 1.710s | 2337.167us | 1 | 1 | 100.00 | |
| sysrst_ctrl_same_csr_outstanding | 3.030s | 4688.807us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 4.440s | 6047.881us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_rw | 1.870s | 2079.605us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 1.710s | 2337.167us | 1 | 1 | 100.00 | |
| sysrst_ctrl_same_csr_outstanding | 3.030s | 4688.807us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| sysrst_ctrl_sec_cm | 73.840s | 42010.920us | 1 | 1 | 100.00 | |
| sysrst_ctrl_tl_intg_err | 23.020s | 42944.847us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_intg_err | 23.020s | 42944.847us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_stress_all_with_rand_reset | 29.370s | 874863.481us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) | 1 test run | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 111469387641643104003307133446190156791859300482778683527985058119365307699859 | 676 |
UVM_INFO @ 18913587710 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 18933587710 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 28994222828 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2f
UVM_INFO @ 28994253131 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1f
|
|