Simulation Results: uart

 
26/08/2026 15:30:29 DVSim: v1.52.0 sha: 31e43cb json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 79.10 %
  • code
  • 91.77 %
  • assert
  • 97.12 %
  • func
  • 48.41 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 96.03 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.890s 443.720us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.690s 107.619us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.770s 11.797us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.400s 266.994us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.650s 51.673us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.810s 23.503us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.770s 11.797us 1 1 100.00
uart_csr_aliasing 0.650s 51.673us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 76.060s 85560.826us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.890s 443.720us 1 1 100.00
uart_tx_rx 76.060s 85560.826us 1 1 100.00
parity_error 2 2 100.00
uart_intr 5.760s 30882.006us 1 1 100.00
uart_rx_parity_err 32.250s 36481.083us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 76.060s 85560.826us 1 1 100.00
uart_intr 5.760s 30882.006us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 17.350s 21469.833us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 40.550s 38641.184us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 23.620s 28207.854us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 5.760s 30882.006us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 5.760s 30882.006us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 5.760s 30882.006us 1 1 100.00
perf 1 1 100.00
uart_perf 148.510s 13242.459us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.280s 2620.838us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.280s 2620.838us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 2.120s 3302.288us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 0.980s 3314.798us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.570s 565.650us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 1.000s 1390.620us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 271.530s 81676.228us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 17.700s 42055.481us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.700s 13.653us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.580s 40.549us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.100s 58.515us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.100s 58.515us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.690s 107.619us 1 1 100.00
uart_csr_rw 0.770s 11.797us 1 1 100.00
uart_csr_aliasing 0.650s 51.673us 1 1 100.00
uart_same_csr_outstanding 0.830s 89.240us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.690s 107.619us 1 1 100.00
uart_csr_rw 0.770s 11.797us 1 1 100.00
uart_csr_aliasing 0.650s 51.673us 1 1 100.00
uart_same_csr_outstanding 0.830s 89.240us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.830s 37.776us 1 1 100.00
uart_tl_intg_err 1.180s 185.479us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.180s 185.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 49.800s 4328.443us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 39688425610991135611263481294590503006021983389433516709187665685959753415492 80
UVM_ERROR @ 295687843 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 295687843 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 295687843 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 1150127843 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 9, clk_pulses: 0
UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_stress_all 64745344007634082542202534243443637155714670855254993233246509759608112920785 89
UVM_ERROR @ 36375800627 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 36375960627 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (53 [0x35] vs 191 [0xbf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 36569960627 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 36570040627 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty