Simulation Results: adc_ctrl

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 71.00 %
  • code
  • 97.82 %
  • assert
  • 96.60 %
  • func
  • 18.59 %
  • line
  • 99.02 %
  • branch
  • 98.45 %
  • cond
  • 94.33 %
  • toggle
  • 100.00 %
  • FSM
  • 97.30 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 12.390s 5992.778us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 3.020s 1187.841us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.810s 328.473us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 53.270s 26446.536us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.660s 413.895us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.550s 450.792us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.810s 328.473us 1 1 100.00
adc_ctrl_csr_aliasing 1.660s 413.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 80.600s 36673.114us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 16.800s 34974.225us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 29.820s 18102.160us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 76.420s 37328.127us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 12.160s 68356.014us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 22.290s 44950.678us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 12.070s 40814.952us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 8.130s 19164.440us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 8.400s 4347.756us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 40.370s 35069.247us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 89.310s 114114.900us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 94.180s 64774.041us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.300s 352.395us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.440s 441.567us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.610s 575.620us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.610s 575.620us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.020s 1187.841us 1 1 100.00
adc_ctrl_csr_rw 1.810s 328.473us 1 1 100.00
adc_ctrl_csr_aliasing 1.660s 413.895us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.530s 5000.198us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 3.020s 1187.841us 1 1 100.00
adc_ctrl_csr_rw 1.810s 328.473us 1 1 100.00
adc_ctrl_csr_aliasing 1.660s 413.895us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.530s 5000.198us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.060s 4303.841us 1 1 100.00
adc_ctrl_tl_intg_err 21.730s 8459.098us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 21.730s 8459.098us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 15.690s 12445.341us 1 1 100.00