Simulation Results: aes/masked

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.59 %
  • code
  • 94.25 %
  • assert
  • 98.23 %
  • func
  • 76.29 %
  • block
  • 94.38 %
  • line
  • 95.99 %
  • branch
  • 87.45 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 98.678us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 98.040us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 111.543us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 3.000s 102.558us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 482.559us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 72.552us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 54.428us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 3.000s 102.558us 1 1 100.00
aes_csr_aliasing 2.000s 72.552us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 98.040us 1 1 100.00
aes_config_error 4.000s 103.452us 1 1 100.00
aes_stress 3.000s 107.731us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 98.040us 1 1 100.00
aes_config_error 4.000s 103.452us 1 1 100.00
aes_stress 3.000s 107.731us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 107.731us 1 1 100.00
aes_b2b 3.000s 152.302us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 107.731us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 98.040us 1 1 100.00
aes_config_error 4.000s 103.452us 1 1 100.00
aes_stress 3.000s 107.731us 1 1 100.00
aes_alert_reset 6.000s 182.656us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 70.319us 1 1 100.00
aes_config_error 4.000s 103.452us 1 1 100.00
aes_alert_reset 6.000s 182.656us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 408.491us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 14.000s 4179.639us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 6.000s 182.656us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 107.731us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 107.731us 1 1 100.00
aes_sideload 4.000s 176.555us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 6.000s 258.234us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 6.000s 133.760us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 54.227us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 78.492us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 78.492us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 111.543us 1 1 100.00
aes_csr_rw 3.000s 102.558us 1 1 100.00
aes_csr_aliasing 2.000s 72.552us 1 1 100.00
aes_same_csr_outstanding 3.000s 132.380us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 111.543us 1 1 100.00
aes_csr_rw 3.000s 102.558us 1 1 100.00
aes_csr_aliasing 2.000s 72.552us 1 1 100.00
aes_same_csr_outstanding 3.000s 132.380us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 85.023us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 5.000s 505.866us 0 1 0.00
aes_control_fi 3.000s 49.686us 1 1 100.00
aes_cipher_fi 3.000s 49.468us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 100.401us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 100.401us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 100.401us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 100.401us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 726.070us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 15.000s 2328.032us 1 1 100.00
aes_tl_intg_err 4.000s 222.106us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 4.000s 222.106us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 6.000s 182.656us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 100.401us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 100.401us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 98.040us 1 1 100.00
aes_stress 3.000s 107.731us 1 1 100.00
aes_alert_reset 6.000s 182.656us 1 1 100.00
aes_core_fi 3.000s 129.647us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 4.000s 103.452us 1 1 100.00
aes_stress 3.000s 107.731us 1 1 100.00
aes_core_fi 3.000s 129.647us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 100.401us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 60.375us 1 1 100.00
aes_stress 3.000s 107.731us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 107.731us 1 1 100.00
aes_sideload 4.000s 176.555us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 60.375us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 60.375us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 60.375us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 60.375us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 60.375us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 107.731us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 107.731us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 5.000s 505.866us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 5.000s 505.866us 0 1 0.00
aes_control_fi 3.000s 49.686us 1 1 100.00
aes_cipher_fi 3.000s 49.468us 1 1 100.00
aes_ctr_fi 3.000s 155.817us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 5.000s 505.866us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 5.000s 505.866us 0 1 0.00
aes_control_fi 3.000s 49.686us 1 1 100.00
aes_cipher_fi 3.000s 49.468us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 49.468us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 5.000s 505.866us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 5.000s 505.866us 0 1 0.00
aes_control_fi 3.000s 49.686us 1 1 100.00
aes_ctr_fi 3.000s 155.817us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 5.000s 505.866us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 5.000s 505.866us 0 1 0.00
aes_control_fi 3.000s 49.686us 1 1 100.00
aes_cipher_fi 3.000s 49.468us 1 1 100.00
aes_ctr_fi 3.000s 155.817us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 6.000s 182.656us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 5.000s 505.866us 0 1 0.00
aes_control_fi 3.000s 49.686us 1 1 100.00
aes_cipher_fi 3.000s 49.468us 1 1 100.00
aes_ctr_fi 3.000s 155.817us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 5.000s 505.866us 0 1 0.00
aes_control_fi 3.000s 49.686us 1 1 100.00
aes_cipher_fi 3.000s 49.468us 1 1 100.00
aes_ctr_fi 3.000s 155.817us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 5.000s 505.866us 0 1 0.00
aes_control_fi 3.000s 49.686us 1 1 100.00
aes_ctr_fi 3.000s 155.817us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 5.000s 505.866us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 5.000s 505.866us 0 1 0.00
aes_control_fi 3.000s 49.686us 1 1 100.00
aes_cipher_fi 3.000s 49.468us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 10.027us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 32370477192362072741598483849004123207493992858057460744704545974802697847866 9723
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 98785967486815092542769948385058911041074197770593425971099185311049266490830 109
UVM_INFO @ 10027095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---