Simulation Results: aes/unmasked

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.85 %
  • code
  • 89.54 %
  • assert
  • 98.11 %
  • func
  • 75.91 %
  • block
  • 89.97 %
  • line
  • 92.47 %
  • branch
  • 81.03 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 59.069us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 95.268us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 3.000s 75.164us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 3.000s 94.430us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 267.335us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 1.000s 71.341us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 144.198us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 3.000s 94.430us 1 1 100.00
aes_csr_aliasing 1.000s 71.341us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 95.268us 1 1 100.00
aes_config_error 3.000s 77.458us 1 1 100.00
aes_stress 3.000s 354.972us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 95.268us 1 1 100.00
aes_config_error 3.000s 77.458us 1 1 100.00
aes_stress 3.000s 354.972us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 354.972us 1 1 100.00
aes_b2b 6.000s 184.049us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 354.972us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 95.268us 1 1 100.00
aes_config_error 3.000s 77.458us 1 1 100.00
aes_stress 3.000s 354.972us 1 1 100.00
aes_alert_reset 2.000s 91.883us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 82.279us 1 1 100.00
aes_config_error 3.000s 77.458us 1 1 100.00
aes_alert_reset 2.000s 91.883us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 53.972us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 749.232us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 91.883us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 354.972us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 354.972us 1 1 100.00
aes_sideload 3.000s 118.482us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 193.932us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 17.000s 647.618us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 58.540us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 4.000s 365.726us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 4.000s 365.726us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 3.000s 75.164us 1 1 100.00
aes_csr_rw 3.000s 94.430us 1 1 100.00
aes_csr_aliasing 1.000s 71.341us 1 1 100.00
aes_same_csr_outstanding 3.000s 59.370us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 3.000s 75.164us 1 1 100.00
aes_csr_rw 3.000s 94.430us 1 1 100.00
aes_csr_aliasing 1.000s 71.341us 1 1 100.00
aes_same_csr_outstanding 3.000s 59.370us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 180.756us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 4.000s 133.181us 0 1 0.00
aes_control_fi 2.000s 192.997us 1 1 100.00
aes_cipher_fi 2.000s 52.898us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 100.536us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 100.536us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 100.536us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 100.536us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 271.250us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 5668.414us 1 1 100.00
aes_tl_intg_err 3.000s 542.329us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 542.329us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 91.883us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 100.536us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 100.536us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 95.268us 1 1 100.00
aes_stress 3.000s 354.972us 1 1 100.00
aes_alert_reset 2.000s 91.883us 1 1 100.00
aes_core_fi 3.000s 71.320us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 77.458us 1 1 100.00
aes_stress 3.000s 354.972us 1 1 100.00
aes_core_fi 3.000s 71.320us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 100.536us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 59.895us 1 1 100.00
aes_stress 3.000s 354.972us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 354.972us 1 1 100.00
aes_sideload 3.000s 118.482us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 59.895us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 59.895us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 59.895us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 59.895us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 59.895us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 354.972us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 354.972us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 133.181us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 133.181us 0 1 0.00
aes_control_fi 2.000s 192.997us 1 1 100.00
aes_cipher_fi 2.000s 52.898us 1 1 100.00
aes_ctr_fi 3.000s 68.961us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 133.181us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 133.181us 0 1 0.00
aes_control_fi 2.000s 192.997us 1 1 100.00
aes_cipher_fi 2.000s 52.898us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 52.898us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 133.181us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 133.181us 0 1 0.00
aes_control_fi 2.000s 192.997us 1 1 100.00
aes_ctr_fi 3.000s 68.961us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 133.181us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 133.181us 0 1 0.00
aes_control_fi 2.000s 192.997us 1 1 100.00
aes_cipher_fi 2.000s 52.898us 1 1 100.00
aes_ctr_fi 3.000s 68.961us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 91.883us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 133.181us 0 1 0.00
aes_control_fi 2.000s 192.997us 1 1 100.00
aes_cipher_fi 2.000s 52.898us 1 1 100.00
aes_ctr_fi 3.000s 68.961us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 133.181us 0 1 0.00
aes_control_fi 2.000s 192.997us 1 1 100.00
aes_cipher_fi 2.000s 52.898us 1 1 100.00
aes_ctr_fi 3.000s 68.961us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 133.181us 0 1 0.00
aes_control_fi 2.000s 192.997us 1 1 100.00
aes_ctr_fi 3.000s 68.961us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 133.181us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 133.181us 0 1 0.00
aes_control_fi 2.000s 192.997us 1 1 100.00
aes_cipher_fi 2.000s 52.898us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 22.000s 1117.025us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 109375604728474322689759758250400820573913803529354316335982339216536747898083 4581
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 3733233158527860511452441003713443992780743913316861017585024394903186339015 1017
UVM_INFO @ 1117025176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---