Simulation Results

Simulation Results: chip

27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
71.38 %

code
76.07 %

assert
96.74 %

func
41.34 %

line
93.68 %

branch
93.28 %

cond
89.52 %

toggle
70.52 %

FSM
33.33 %

Validation stages

V1		94.12%
V2		85.17%
V2S		100.00%
V3		64.00%
unmapped		12.50%

16/17 passed

94.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				3	3	100.00
	chip_sw_example_rom	103.180s	2256.086us	1	1	100.00
	chip_sw_example_manufacturer	209.350s	2172.706us	1	1	100.00
	chip_sw_example_concurrency	178.460s	2287.445us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	646.140s	12307.704us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	599.370s	9524.188us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	1224.380s	17375.193us	1	1	100.00
csr_aliasing				0	1	0.00
	chip_csr_aliasing	10800.152s	0.000us	0	1	0.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	1042.500s	15354.205us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				1	2	50.00
	chip_csr_aliasing	10800.152s	0.000us	0	1	0.00
	chip_csr_rw	599.370s	9524.188us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	8.420s	199.733us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	336.080s	3847.778us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	336.080s	3847.778us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	336.080s	3847.778us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	522.260s	4205.631us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	522.260s	4205.631us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	452.600s	4683.352us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	478.130s	4585.993us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	412.700s	4403.560us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1247.950s	8187.831us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1278.390s	8023.058us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	754.690s	8454.237us	1	1	100.00

224/263 passed

85.17 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	461.810s	9207.890us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	461.810s	9207.890us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	250.310s	2963.195us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	439.270s	5613.343us	1	1	100.00
chip_sw_sleep_pin_retention				0	1	0.00
	chip_sw_sleep_pin_retention	206.900s	2606.320us	0	1	0.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	441.240s	5639.948us	1	1	100.00
	chip_tap_straps_testunlock0	249.440s	4100.364us	1	1	100.00
	chip_tap_straps_rma	485.100s	6683.810us	1	1	100.00
	chip_tap_straps_prod	143.390s	2365.776us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	537.050s	5445.040us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	537.050s	5445.040us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	673.830s	7406.978us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1697.940s	12369.485us	0	1	0.00
chip_sw_ast_sys_clk_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4447.020s	19064.516us	1	1	100.00
	chip_sw_aes_enc_jitter_en	210.590s	2450.220us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	835.420s	6388.895us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	239.420s	3192.297us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	2195.430s	13043.962us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	286.710s	2959.846us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	411.380s	3634.747us	1	1	100.00
	chip_sw_clkmgr_jitter	168.730s	2409.274us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	274.530s	3197.188us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				1	2	50.00
	chip_sw_sensor_ctrl_alert	439.470s	4849.531us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	182.780s	2714.443us	0	1	0.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	259.860s	2780.457us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				0	1	0.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	182.780s	2714.443us	0	1	0.00
chip_sw_smoketest				16	16	100.00
	chip_sw_aes_smoketest	207.680s	2853.302us	1	1	100.00
	chip_sw_aon_timer_smoketest	268.910s	3311.279us	1	1	100.00
	chip_sw_clkmgr_smoketest	253.780s	2555.337us	1	1	100.00
	chip_sw_csrng_smoketest	188.570s	2243.556us	1	1	100.00
	chip_sw_entropy_src_smoketest	900.250s	6467.274us	1	1	100.00
	chip_sw_gpio_smoketest	312.890s	3408.400us	1	1	100.00
	chip_sw_hmac_smoketest	266.530s	3147.423us	1	1	100.00
	chip_sw_kmac_smoketest	233.850s	2393.004us	1	1	100.00
	chip_sw_otbn_smoketest	1110.270s	6576.757us	1	1	100.00
	chip_sw_pwrmgr_smoketest	373.140s	6117.334us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	434.110s	6361.162us	1	1	100.00
	chip_sw_rv_plic_smoketest	177.580s	2225.192us	1	1	100.00
	chip_sw_rv_timer_smoketest	236.350s	2610.149us	1	1	100.00
	chip_sw_rstmgr_smoketest	169.870s	2571.408us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	210.100s	3034.437us	1	1	100.00
	chip_sw_uart_smoketest	209.440s	2529.452us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	190.490s	2940.940us	1	1	100.00
chip_sw_rom_functests				1	1	100.00
	rom_keymgr_dpe_functest	435.410s	4133.727us	1	1	100.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	21048.750s	127745.406us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3706.760s	14783.311us	1	1	100.00
chip_sw_rom_raw_unlock				1	1	100.00
	rom_raw_unlock	465.580s	9028.377us	1	1	100.00
chip_sw_power_idle_load				1	1	100.00
	chip_sw_power_idle_load	472.120s	4066.350us	1	1	100.00
chip_sw_power_sleep_load				1	1	100.00
	chip_sw_power_sleep_load	466.660s	9761.987us	1	1	100.00
chip_sw_exit_test_unlocked_bootstrap				0	1	0.00
	chip_sw_exit_test_unlocked_bootstrap	13200.151s	0.000us	0	1	0.00
tl_d_oob_addr_access				1	1	100.00
	chip_tl_errors	415.570s	9985.662us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	chip_tl_errors	415.570s	9985.662us	1	1	100.00
tl_d_outstanding_access				3	4	75.00
	chip_csr_aliasing	10800.152s	0.000us	0	1	0.00
	chip_same_csr_outstanding	2839.930s	28364.598us	1	1	100.00
	chip_csr_hw_reset	646.140s	12307.704us	1	1	100.00
	chip_csr_rw	599.370s	9524.188us	1	1	100.00
tl_d_partial_access				3	4	75.00
	chip_csr_aliasing	10800.152s	0.000us	0	1	0.00
	chip_same_csr_outstanding	2839.930s	28364.598us	1	1	100.00
	chip_csr_hw_reset	646.140s	12307.704us	1	1	100.00
	chip_csr_rw	599.370s	9524.188us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	22.260s	570.123us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	6.250s	43.473us	1	1	100.00
	xbar_smoke_large_delays	57.120s	8396.432us	1	1	100.00
	xbar_smoke_slow_rsp	44.670s	3743.676us	1	1	100.00
	xbar_random_zero_delays	18.510s	196.219us	1	1	100.00
	xbar_random_large_delays	176.690s	24726.459us	1	1	100.00
	xbar_random_slow_rsp	52.630s	4866.616us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	12.060s	98.711us	1	1	100.00
	xbar_error_and_unmapped_addr	29.140s	299.438us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	8.720s	106.485us	1	1	100.00
	xbar_error_and_unmapped_addr	29.140s	299.438us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	35.510s	472.293us	1	1	100.00
	xbar_access_same_device_slow_rsp	604.770s	57535.964us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	28.060s	1185.454us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	239.480s	3751.916us	1	1	100.00
	xbar_stress_all_with_error	34.440s	426.211us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	276.870s	6812.375us	1	1	100.00
	xbar_stress_all_with_reset_error	197.970s	2640.294us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3706.760s	14783.311us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	3173.030s	23614.147us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	4076.290s	28406.149us	1	1	100.00
rom_e2e_boot_policy_valid				15	15	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2983.790s	11232.903us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	4109.670s	16335.205us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	3956.520s	15310.913us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	4066.340s	16672.305us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	3844.160s	15504.320us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	3113.500s	13671.429us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	3988.620s	16155.720us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	3942.590s	16226.573us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	4007.340s	15405.292us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	3871.800s	14697.852us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	5219.780s	18190.463us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	6651.340s	24776.290us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	6387.940s	24667.018us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	6696.410s	24144.089us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	6364.990s	23976.900us	1	1	100.00
rom_e2e_sigverify_always				14	15	93.33
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	5447.760s	23912.744us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	6481.630s	23573.702us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	6330.560s	22744.462us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	165.270s	2748.189us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	6333.430s	21460.246us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	2874.950s	11172.154us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	3954.000s	22644.761us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	3800.830s	21298.313us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	3734.960s	21512.808us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	3498.860s	14125.301us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	2770.200s	10500.179us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	3429.630s	13776.533us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	4537.560s	42843.340us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	3765.370s	22421.207us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	3818.230s	21404.891us	1	1	100.00
rom_e2e_asm_init				5	5	100.00
	rom_e2e_asm_init_test_unlocked0	2856.300s	11388.003us	1	1	100.00
	rom_e2e_asm_init_dev	4231.470s	16112.772us	1	1	100.00
	rom_e2e_asm_init_prod	3879.350s	16721.959us	1	1	100.00
	rom_e2e_asm_init_prod_end	3801.780s	15822.902us	1	1	100.00
	rom_e2e_asm_init_rma	3642.740s	16238.141us	1	1	100.00
rom_e2e_keymgr_dpe_init				3	3	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_meas	7407.680s	29462.323us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_no_meas	7740.770s	30220.405us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas	7360.200s	31233.352us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3834.720s	15705.153us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.326s	0.000us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.326s	0.000us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	229.900s	3106.427us	1	1	100.00
	chip_sw_aes_enc_jitter_en	210.590s	2450.220us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	244.110s	2186.152us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	205.380s	2569.633us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1608.050s	9451.857us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	295.000s	3244.568us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	494.200s	5581.979us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	514.340s	5692.837us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	559.450s	4917.097us	1	1	100.00
	chip_plic_all_irqs_10	335.610s	2893.629us	1	1	100.00
	chip_plic_all_irqs_20	508.810s	4594.813us	1	1	100.00
chip_sw_alert_handler_entropy				0	1	0.00
	chip_sw_alert_handler_entropy	273.800s	2983.924us	0	1	0.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1078.140s	10818.738us	1	1	100.00
chip_sw_alert_handler_ping_timeout				0	1	0.00
	chip_sw_alert_handler_ping_timeout	270.460s	3191.918us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	171.360s	2576.892us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	255.810s	2807.088us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1131.250s	7785.301us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1345.490s	7528.400us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	970.540s	7789.871us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10660.670s	254915.111us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	304.710s	3756.160us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	373.140s	6117.334us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	304.710s	3756.160us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	560.860s	7382.495us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	560.860s	7382.495us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	351.840s	6484.373us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	452.430s	4033.422us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	762.090s	5966.518us	1	1	100.00
	chip_sw_aes_idle	205.380s	2569.633us	1	1	100.00
	chip_sw_hmac_enc_idle	222.770s	2998.899us	1	1	100.00
	chip_sw_kmac_idle	208.860s	2737.139us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	335.340s	3947.081us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	283.650s	3977.957us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	418.810s	4626.741us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	361.030s	4231.479us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	1267.770s	11156.162us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	455.930s	4105.454us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	491.390s	4542.167us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	522.990s	3824.307us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	530.570s	4962.418us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	528.480s	4461.301us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	467.750s	4558.868us	1	1	100.00
	chip_sw_ast_clk_outputs	673.830s	7406.978us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	757.060s	12444.174us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	522.990s	3824.307us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	530.570s	4962.418us	1	1	100.00
chip_sw_clkmgr_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4447.020s	19064.516us	1	1	100.00
	chip_sw_aes_enc_jitter_en	210.590s	2450.220us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	835.420s	6388.895us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	239.420s	3192.297us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	2195.430s	13043.962us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	286.710s	2959.846us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	411.380s	3634.747us	1	1	100.00
	chip_sw_clkmgr_jitter	168.730s	2409.274us	1	1	100.00
chip_sw_clkmgr_extended_range				8	8	100.00
	chip_sw_clkmgr_jitter_reduced_freq	179.820s	2871.814us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4691.570s	26465.949us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	221.590s	2765.753us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	226.010s	3162.306us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1286.820s	9738.068us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	286.550s	3787.927us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	402.080s	4793.017us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	17471.230s	168120.174us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	673.830s	7406.978us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				0	1	0.00
	chip_sw_clkmgr_sleep_frequency	437.540s	4074.736us	0	1	0.00
chip_sw_clkmgr_reset_frequency				0	1	0.00
	chip_sw_clkmgr_reset_frequency	587.830s	10357.540us	0	1	0.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	514.340s	5692.837us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1131.250s	7785.301us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2689.460s	24490.407us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	471.160s	4470.540us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	805.050s	8199.688us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	226.790s	2454.929us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	3992.470s	18539.667us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	179.370s	2344.179us	1	1	100.00
	chip_sw_edn_entropy_reqs	1127.760s	7408.335us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	179.370s	2344.179us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2689.460s	24490.407us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	170.390s	2417.733us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	215.730s	2445.616us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	239.420s	3192.297us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	222.770s	2998.899us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1241.630s	8374.995us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	2206.420s	12010.100us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	582.270s	5187.001us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	477.180s	4656.656us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	599.370s	5272.176us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	399.170s	4131.192us	1	1	100.00
chip_sw_keymgr_dpe_key_derivation				2	2	100.00
	chip_sw_keymgr_dpe_key_derivation	1167.100s	7662.277us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	2195.430s	13043.962us	1	1	100.00
chip_sw_keymgr_dpe_sideload_kmac				1	1	100.00
	chip_sw_keymgr_dpe_sideload_kmac	1509.870s	9406.449us	1	1	100.00
chip_sw_keymgr_dpe_sideload_aes				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1608.050s	9451.857us	1	1	100.00
chip_sw_keymgr_dpe_sideload_otbn				0	1	0.00
	chip_sw_keymgr_dpe_sideload_otbn	3600.165s	0.000us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	210.100s	2347.918us	1	1	100.00
	chip_sw_kmac_mode_kmac	209.320s	2682.378us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	286.710s	2959.846us	1	1	100.00
chip_sw_kmac_app_keymgr_dpe				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1167.100s	7662.277us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	1803.140s	25584.928us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	563.300s	9979.305us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1895.470s	9778.449us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	208.860s	2737.139us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	494.200s	5581.979us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	441.240s	5639.948us	1	1	100.00
	chip_tap_straps_rma	485.100s	6683.810us	1	1	100.00
	chip_tap_straps_prod	143.390s	2365.776us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	179.740s	2673.009us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	1803.140s	25584.928us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	1803.140s	25584.928us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	1803.140s	25584.928us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_prod	2197.150s	12322.301us	1	1	100.00
chip_sw_lc_ctrl_broadcast				18	21	85.71
	chip_sw_rram_rma_unlocked	397.640s	10010.260us	0	1	0.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	324.280s	2916.573us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	656.600s	6308.282us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	728.690s	6477.272us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	621.130s	5317.435us	0	1	0.00
	chip_sw_lc_ctrl_transition	1803.140s	25584.928us	1	1	100.00
	chip_sw_rram_ctrl_lc_rw_en	386.110s	4047.848us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1167.100s	7662.277us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	808.530s	22662.047us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	556.270s	6794.098us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	757.060s	12444.174us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	455.930s	4105.454us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	491.390s	4542.167us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	522.990s	3824.307us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	530.570s	4962.418us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	528.480s	4461.301us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	467.750s	4558.868us	1	1	100.00
	chip_tap_straps_dev	441.240s	5639.948us	1	1	100.00
	chip_tap_straps_rma	485.100s	6683.810us	1	1	100.00
	chip_tap_straps_prod	143.390s	2365.776us	1	1	100.00
	chip_rv_dm_lc_disabled	69.080s	2561.762us	0	1	0.00
chip_lc_scrap				2	4	50.00
	chip_sw_lc_ctrl_rma_to_scrap	407.920s	5405.935us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	381.640s	7961.598us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	538.260s	9962.424us	0	1	0.00
	chip_sw_lc_ctrl_rand_to_scrap	514.970s	9578.433us	0	1	0.00
chip_lc_test_locked				0	2	0.00
	chip_sw_lc_walkthrough_testunlocks	3600.168s	0.000us	0	1	0.00
	chip_rv_dm_lc_disabled	69.080s	2561.762us	0	1	0.00
chip_sw_lc_walkthrough				1	5	20.00
	chip_sw_lc_walkthrough_dev	1624.500s	19913.394us	0	1	0.00
	chip_sw_lc_walkthrough_prod	1999.190s	20955.249us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	1294.920s	14839.520us	1	1	100.00
	chip_sw_lc_walkthrough_rma	876.770s	11529.117us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	3600.168s	0.000us	0	1	0.00
chip_sw_lc_ctrl_volatile_raw_unlock				3	3	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock	234.060s	4243.126us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	227.770s	3988.332us	1	1	100.00
	rom_volatile_raw_unlock	267.680s	4569.281us	1	1	100.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	4069.930s	17988.162us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4447.020s	19064.516us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	762.090s	5966.518us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	762.090s	5966.518us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	762.090s	5966.518us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	354.530s	3117.410us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	1803.140s	25584.928us	1	1	100.00
chip_sw_otp_ctrl_keys				3	4	75.00
	chip_sw_otbn_mem_scramble	354.530s	3117.410us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1167.100s	7662.277us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	466.120s	4381.637us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.160s	0.000us	0	1	0.00
chip_sw_otp_ctrl_entropy				3	4	75.00
	chip_sw_otbn_mem_scramble	354.530s	3117.410us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1167.100s	7662.277us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	466.120s	4381.637us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.160s	0.000us	0	1	0.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	1803.140s	25584.928us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	578.060s	5622.176us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	179.740s	2673.009us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				4	5	80.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	324.280s	2916.573us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	656.600s	6308.282us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	728.690s	6477.272us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	621.130s	5317.435us	0	1	0.00
	chip_sw_lc_ctrl_transition	1803.140s	25584.928us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	1015.610s	7628.923us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	322.300s	5920.543us	1	1	100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	208.180s	3032.499us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	162.620s	2617.781us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	596.190s	8032.463us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_por_reset	393.110s	4993.398us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1210.480s	23140.894us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				2	2	100.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	1222.690s	13943.357us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	560.860s	7382.495us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	276.930s	2924.213us	0	1	0.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	410.260s	4452.326us	1	1	100.00
chip_sw_pwrmgr_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	322.300s	5920.543us	1	1	100.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	322.800s	3626.330us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	255.440s	3831.870us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	469.930s	6609.915us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	205.960s	2800.075us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	460.330s	7293.176us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	689.410s	6098.052us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	954.970s	9231.858us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1691.720s	27032.199us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	231.200s	2890.376us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	514.340s	5692.837us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	808.530s	22662.047us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	808.530s	22662.047us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	954.970s	9231.858us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	460.330s	7293.176us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	410.260s	4452.326us	1	1	100.00
	chip_sw_pwrmgr_smoketest	373.140s	6117.334us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	400.780s	4900.200us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	418.860s	4702.893us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	441.600s	4906.823us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1078.140s	10818.738us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	230.800s	2611.449us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	514.340s	5692.837us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1345.490s	7528.400us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	601.770s	4313.611us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	644.170s	4531.832us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	259.040s	3354.247us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				0	1	0.00
	chip_sw_rv_core_ibex_icache_invalidate	3600.160s	0.000us	0	1	0.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	418.860s	4702.893us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	418.860s	4702.893us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	249.260s	2664.118us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	1496.520s	19897.023us	1	1	100.00
chip_jtag_mem_access				0	1	0.00
	chip_jtag_mem_access	85.560s	2605.136us	0	1	0.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	400.780s	4900.200us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	290.750s	3187.380us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	197.780s	2750.532us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	485.100s	6683.810us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	69.080s	2561.762us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	559.450s	4917.097us	1	1	100.00
	chip_plic_all_irqs_10	335.610s	2893.629us	1	1	100.00
	chip_plic_all_irqs_20	508.810s	4594.813us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	189.640s	3203.808us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	256.500s	3163.319us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3706.760s	14783.311us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	369.740s	4125.243us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	263.790s	3012.150us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	270.900s	3568.473us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	260.690s	3163.698us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	466.120s	4381.637us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	411.380s	3634.747us	1	1	100.00
chip_sw_sleep_sram_ret_contents				0	2	0.00
	chip_sw_sleep_sram_ret_contents_no_scramble	236.220s	2781.345us	0	1	0.00
	chip_sw_sleep_sram_ret_contents_scramble	210.780s	3370.407us	0	1	0.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	556.270s	6794.098us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	514.340s	5692.837us	1	1	100.00
	chip_sw_data_integrity_escalation	537.050s	5445.040us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	689.410s	6098.052us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1027.270s	23424.440us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	216.810s	2595.505us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	294.820s	3998.582us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	446.110s	4390.766us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1027.270s	23424.440us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1027.270s	23424.440us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2928.780s	20250.791us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2928.780s	20250.791us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	423.850s	5860.267us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3600.326s	0.000us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	214.790s	2759.775us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	175.520s	2915.372us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	360.560s	4075.179us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	412.570s	4043.138us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	977.900s	8193.332us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	6719.970s	31415.423us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	2137.990s	11755.612us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	225.550s	2877.309us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	233.270s	2547.285us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	103.820s	1768.483us	1	1	100.00

16/25 passed

64.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	12969.820s	72480.935us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1456.280s	6505.853us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	99.870s	2002.750us	0	1	0.00
	rom_e2e_jtag_debug_dev	84.540s	1912.227us	0	1	0.00
	rom_e2e_jtag_debug_rma	99.640s	1910.275us	0	1	0.00
rom_e2e_jtag_inject				1	3	33.33
	rom_e2e_jtag_inject_test_unlocked0	363.960s	5075.717us	1	1	100.00
	rom_e2e_jtag_inject_dev	117.880s	2185.605us	0	1	0.00
	rom_e2e_jtag_inject_rma	127.670s	2287.933us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	152.774s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	317.420s	2943.509us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	410.080s	2803.078us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	1224.940s	5728.562us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1639.540s	9141.088us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	279.860s	2676.804us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	358.220s	3237.096us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	410.620s	5624.408us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	370.810s	4850.127us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	954.970s	9231.858us	1	1	100.00
chip_sw_rom_ctrl_digests				1	1	100.00
	chip_sw_kmac_app_rom	563.300s	9979.305us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	99.870s	2002.750us	0	1	0.00
	rom_e2e_jtag_debug_dev	84.540s	1912.227us	0	1	0.00
	rom_e2e_jtag_debug_rma	99.640s	1910.275us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	420.320s	4581.584us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	514.340s	5692.837us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	6234.690s	37881.662us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	6234.690s	37881.662us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				0	1	0.00
	chip_sw_spi_device_pinmux_sleep_retention	199.280s	2808.341us	0	1	0.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	522.260s	4205.631us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3258.430s	18776.175us	1	1	100.00

unmapped

1/8 passed

12.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	8	12.50
	chip_sw_rstmgr_rst_cnsty_escalation	51.630s	10.380us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	110.580s	2356.243us	0	1	0.00
	chip_sw_otp_ctrl_descrambling	240.210s	2972.291us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	214.870s	3218.439us	0	1	0.00
	chip_sw_pwrmgr_sleep_wake_5_bug	10.792s	0.000us	0	1	0.00
	ate_bootstrap_flash_erase	802.840s	10010.140us	0	1	0.00
	ate_bootstrap_one_frame	10800.144s	0.000us	0	1	0.00
	ate_bootstrap_disjoint	10800.153s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error				14 test runs
	chip_sw_sleep_pin_retention	82309920996743674693342833320443807096823957271615802685910427192875604238950	379	UVM_INFO @ 2606.320212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_spi_device_pinmux_sleep_retention	90175030808999826401081215961438354499373649753807455690920620461698560965644	374	UVM_INFO @ 2808.341496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	95866311576018184973526050903836824929042149371736064717370802820286101612861	392	UVM_INFO @ 7293.176004 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	72932898786671074299132186612060431855205780047616827702854881570907326772003	377	UVM_INFO @ 2924.213228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_por_reset	33560923988633016274894433529506659900591337897358387582859379196225151661997	388	UVM_INFO @ 4993.397864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	86602643726490668480811751984726575048914901136019915028675823588434924153097	379	UVM_INFO @ 3831.869826 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_no_scramble	51286538584841303557637303880752164398597532571264756176429641420774080137116	377	UVM_INFO @ 2781.345384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_scramble	70795656559358496849851709443380193612711882072248239897300415479528843463196	381	UVM_INFO @ 3370.406854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	85711091912389507757053459176996932552031763613726449617665845288014810649467	372	UVM_INFO @ 2714.442864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_clkmgr_sleep_frequency	1525485688342116053589411590311817690771488130031011522397624708028533309585	407	UVM_INFO @ 4074.735720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	10266883427700125834030979506864657473340076454212687162785706646303712525506	374	UVM_INFO @ 2617.780984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_lowpower_cancel	14405556832624429829550471843452026309113383150813941083303312413289576678396	372	UVM_INFO @ 3218.439480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_wake_ups	111495473654960433851037703980121826309792042152499966186929841019581602490919	373	UVM_INFO @ 3032.499340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_dm_access_after_wakeup	42452909211899418917054585746845624841545008744405349839821075190711558993865	390	UVM_INFO @ 2750.532266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				8 test runs
	chip_csr_aliasing	91290693890282740568153133975010503954634780999304713962880809689433115094471	None
	chip_sw_exit_test_unlocked_bootstrap	46712653626464569308489917308304609113803421048773984329558075459126937337304	None
	chip_sw_lc_walkthrough_testunlocks	14588634054210153310781629958109340743355730316862623640401353907436944365065	None
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	79693255544581051670846841978300014571022874976668754154406351356300531574165	None
	chip_sw_keymgr_dpe_sideload_otbn	8731744500591691246782187426945199474700973665048775769989580051358107050375	None
	chip_sw_rv_core_ibex_icache_invalidate	41380577255688457279965452725384452389179761921382270057632900981063013750165	None
	ate_bootstrap_one_frame	70373665306746277097373753743830195470990687171287932767288988357543332972500	None
	ate_bootstrap_disjoint	42995306611636307912510630730206246519250554122813106343965527140728161248990	None
Error-[NOA] Null object access				4 test runs
	chip_sw_otp_ctrl_rot_auth_config	95525716647960304856337845461262430149744462984949193588869164618824150820223	383	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	41537174705715182163736670096418451111111156059069929968817038301462490785644	403	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	42582344087457600074203658574003325302330550838570513917881502597665664951079	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	103670679436614521372967040615757860889221370550214902168660542925430263905407	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	73903664019091205474411493740220426610443630384077503816581460199494993211324	433	UVM_INFO @ 19913.393635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	52416086059252181384921009584739004612472034409496638837117319198977502472048	433	UVM_INFO @ 20955.249115 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	99582991620518544456741014284700341732153036264343483773663961193967928662799	405	UVM_INFO @ 11529.116960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error				3 test runs
	chip_sw_alert_handler_ping_timeout	44283437357187983119955535445484700030285103998734432664412702067215688056694	371	UVM_INFO @ 3191.917632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_alert_handler_lpg_sleep_mode_pings	66673638814042540023369074846093669823685230702078029116511538759458411661686	373	UVM_INFO @ 2807.088260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_alert_handler_entropy	3749264025571330558873164685745927422679334953855929121265718677760894375297	457	UVM_INFO @ 2983.924124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [] vs [*])				3 test runs
	rom_e2e_jtag_debug_test_unlocked0	35429666936712108169181848086790013217363334824145066232167702765081556257991	359	UVM_INFO @ 2002.750000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_dev	99555690786358167621369404392070118262666212747190860253442525069498366064283	359	UVM_INFO @ 1912.227500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_rma	76518508635064179151324925084753592487293674367657388025581407926637381589773	359	UVM_INFO @ 1910.275000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl				2 test runs
	chip_sw_lc_ctrl_test_locked0_to_scrap	91326146217957354039587724136748201633925567426873153489439181537320131108503	375	UVM_INFO @ 9962.424436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_ctrl_rand_to_scrap	41587302029872416372345937224755794283675005363835566123608026458539483693441	375	UVM_INFO @ 9578.433414 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	113144143675817200426227740736260387820745001472067311982164501598694504590094	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	46094091245009060348192622059686887115572428895551566865135295232643764446289	None	Another command (pid=587132) is running. Waiting for it to complete on the server (server_pid=192229)... Another command (pid=595214) is running. Waiting for it to complete on the server (server_pid=192229)... Another command (pid=584254) is running. Waiting for it to complete on the server (server_pid=192229)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	58905710002454961908325022770773473021216068595769711657150851870236592740162	365	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch				1 test run
	chip_sw_spi_device_pass_through_collision	26759884649373929217798036094719153361909812856189885258160571086038593813286	393	host_rsp: ------------------------------------------------------------------------- Name Type Size Value -------------------------------------------------------------------------
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred!				1 test run
	chip_sw_rram_rma_unlocked	84276787090873394085770546154112386930408670678146273798647068758430582251032	337	UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	24496583800716589961063532382041633466048383557093713399236337170452299789774	404	UVM_INFO @ 5317.434605 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:715)] CHECK-fail: Alert handler NMI state not expected:				1 test run
	chip_sw_otp_ctrl_escalation	58802676098318958799358301958161455542020835011091543417568484653734482938746	379	alert_enable:1 alert_raised:0 UVM_INFO @ 3237.095897 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	26753673787476873782024543328125710565762280175851588299281534008986889295551	377	UVM_ERROR @ 2800.074860 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 2800.074860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:415)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	108383310889017185844831121590928387060768185632356985683974460719113808020778	371	UVM_INFO @ 3244.568475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	6697877335250375524211684235628052890837689846318486518575047366758111287763	373	UVM_INFO @ 2576.891986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_hmac_multistream	55298457045801406486555354831511374588409340182316890831094289474467531021991	437	UVM_INFO @ 12010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.				1 test run
	chip_sw_clkmgr_reset_frequency	47684596016427879681005133346851488953875013537029120185584203178465193754131	400	UVM_INFO @ 10357.539904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	58084009426127788155411357921647120185262184587812155172602958845043794634365	407	UVM_INFO @ 2943.508934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts!				1 test run
	chip_jtag_mem_access	22540957499174630769567314342662602042876491529795318325887547193837275339007	5365	UVM_INFO @ 2605.135852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	63255627769335811988178183846558598540403250189891774287549258417969001381797	292	UVM_INFO @ 2561.762034 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	64761668578094557888538825330044403157069092994035659702079271044468935715216	391	UVM_INFO @ 12369.485027 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	3625667171574545366035530562894087075618855824586979180647450497328968003236	339	UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'				1 test run
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	42086672936318202089061356803511626413630318070361819326936951163799768402926	447	UVM_ERROR @ 2748.188925 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M UVM_INFO @ 2748.188925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---