Simulation Results: clkmgr

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 93.51 %
  • code
  • 98.25 %
  • assert
  • 95.48 %
  • func
  • 86.79 %
  • line
  • 99.00 %
  • branch
  • 98.64 %
  • cond
  • 94.40 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
92.86%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.970s 45.931us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.140s 22.899us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.980s 18.262us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.650s 1290.361us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.130s 24.829us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.590s 41.935us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.980s 18.262us 1 1 100.00
clkmgr_csr_aliasing 1.130s 24.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.000s 37.518us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.790s 227.648us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.050s 27.529us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.140s 45.482us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.970s 45.931us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 17.407s 0.000us 0 1 0.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 9.240s 1816.113us 1 1 100.00
frequency_overflow 0 1 0.00
clkmgr_frequency 17.407s 0.000us 0 1 0.00
stress_all 1 1 100.00
clkmgr_stress_all 27.000s 8692.328us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.190s 46.605us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.560s 119.923us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.560s 119.923us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.140s 22.899us 1 1 100.00
clkmgr_csr_rw 0.980s 18.262us 1 1 100.00
clkmgr_csr_aliasing 1.130s 24.829us 1 1 100.00
clkmgr_same_csr_outstanding 1.400s 47.842us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.140s 22.899us 1 1 100.00
clkmgr_csr_rw 0.980s 18.262us 1 1 100.00
clkmgr_csr_aliasing 1.130s 24.829us 1 1 100.00
clkmgr_same_csr_outstanding 1.400s 47.842us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 1.430s 54.539us 0 1 0.00
clkmgr_tl_intg_err 2.510s 98.799us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 3.430s 577.194us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 3.430s 577.194us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 3.430s 577.194us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 3.430s 577.194us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 50.340s 10019.749us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.510s 98.799us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 17.407s 0.000us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 9.240s 1816.113us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 3.430s 577.194us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.200s 32.111us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.680s 273.659us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.280s 28.212us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.220s 31.935us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.190s 27.844us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.980s 18.262us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.430s 54.539us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.980s 18.262us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.980s 18.262us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.430s 54.539us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.360s 533.271us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 23.100s 3561.508us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
clkmgr_frequency 47804378978233495164008745923115998182329822477197966447220076734706628699278 None
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Compiler version X-2025.06-SP2-1_Full64; Runtime version X-2025.06-SP2-1_Full64; Aug 27 15:33 2026
Feature removed during lmreread, or wrong
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
UVM_FATAL (cip_base_vseq__shadow_reg_errors.svh:332) [clkmgr_common_vseq] io_div4_meas_ctrl_shadowed update_err alert timeout 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 7828606765957590966247682466819500576654013448001284065142426465147130960978 81
UVM_INFO @ 10019749079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 37179342723793842136680613222644277789549773492065444103175186756237106401500 123
UVM_INFO @ 54538635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---