Simulation Results: edn/edn0

 
27/08/2026 15:30:28 DVSim: v1.52.0 sha: dea2a08 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 83.37 %
  • code
  • 76.56 %
  • assert
  • 94.79 %
  • func
  • 78.77 %
  • line
  • 96.14 %
  • branch
  • 86.75 %
  • cond
  • 82.30 %
  • toggle
  • 69.78 %
  • FSM
  • 47.85 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.950s 105.779us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.130s 29.628us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.930s 57.895us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 6.020s 310.793us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.170s 14.613us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.810s 37.399us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.930s 57.895us 1 1 100.00
edn_csr_aliasing 1.170s 14.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.410s 53.956us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.410s 53.956us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.410s 53.956us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.090s 25.944us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.650s 31.050us 1 1 100.00
errs 1 1 100.00
edn_err 1.200s 34.598us 1 1 100.00
disable 2 2 100.00
edn_disable 1.190s 51.663us 1 1 100.00
edn_disable_auto_req_mode 1.320s 32.417us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.800s 271.279us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.980s 50.616us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.220s 46.397us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.430s 218.437us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.430s 218.437us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.130s 29.628us 1 1 100.00
edn_csr_rw 0.930s 57.895us 1 1 100.00
edn_csr_aliasing 1.170s 14.613us 1 1 100.00
edn_same_csr_outstanding 1.110s 22.010us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.130s 29.628us 1 1 100.00
edn_csr_rw 0.930s 57.895us 1 1 100.00
edn_csr_aliasing 1.170s 14.613us 1 1 100.00
edn_same_csr_outstanding 1.110s 22.010us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.050s 2138.177us 1 1 100.00
edn_tl_intg_err 2.550s 119.443us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.280s 71.768us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.650s 31.050us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.050s 2138.177us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.050s 2138.177us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.050s 2138.177us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.050s 2138.177us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.650s 31.050us 1 1 100.00
edn_sec_cm 6.050s 2138.177us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.650s 31.050us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.550s 119.443us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 36.330s 1873.201us 1 1 100.00